US5548797A
Expired / Lapsed
US
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Digital clock pulse positioning circuit for delaying a signal input by a fist time duration and a second time duration to provide a positioned clock signal
Assignee: International Business Machines Corp
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Filing: 1994-10-03
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Granted: 1996-08-20
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Expires: 2014-10-03
Abstract
Abstract An input/output channel controller includes a storage array for temporarily storing data and multiple clocks to access or update the data. One or more array clock signals are generated from a system clock combined with other clock signals to generate a single clock signal which is positioned in time by a clock positioning circuit to accommodate circuit throughput delay variations and to effectively reduce hold time to zero. Storage arrays may be clocked at significantly higher frequencies and arrays may have multiple gated clocks without incurring the hold time problems.
Inventors
- 👤 Ravi K. Arimilli
- 👤 John S. Dodson
- 👤 Jerry D. Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:35
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3869; H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/15026
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
153 words
A data processing system comprising: one or more processors; a system bus; a memory system; a system control unit; one or more input/output channel control units (IOCC), each of said IOCC units comprising a storage array and a digital clock positioning circuit to position clock signals output from said digital clock pulse positioning circuit to be active when information inputs to said array are stable; wherein said digital clock pulse positioning circuit further comprises: a first digital delay circuit for delaying an input signal by a first time duration T1; a second digital delay circuit responsive to an output of said first digital delay circuit for delaying a signal input to said second digital delay circuit by a second time duration T2; and circuit means responsive to an output of said first digital delay circuit and an output of said second digital delay circuit for providing a positioned clock signal for said array.
Claim 2
Dependent Claim
153 words
A data processing system comprising: one or more processors; a system bus; a memory system; a system control unit; one or more input/output channel control units (IOCC), each of said IOCC units comprising a storage array and a digital clock positioning circuit to position clock signals output from said digital clock pulse positioning circuit to be active when information inputs to said array are stable; wherein said digital clock pulse positioning circuit further comprises: a first digital delay circuit for delaying an input signal by a first time duration T1; a second digital delay circuit responsive to an output of said first digital delay circuit for delaying a signal input to said second digital delay circuit by a second time duration T2; and circuit means responsive to an output of said first digital delay circuit and an output of said second digital delay circuit for providing a positioned clock signal for said array.
Claim 3
Dependent Claim
31 words
A data processing system, according to claim 1, further comprising circuit means for selecting one of a plurality of clock signals as an input to said digital clock pulse positioning circuit.
Claim 4
Dependent Claim
84 words
A data processing system, according to claim 1, wherein said digital clock pulse positioning circuit further comprises: a third digital delay circuit responsive to an output of said second digital delay circuit for delaying a signal input to said third digital delay circuit by a third time duration; and a selection circuit for selecting an output of said second digital delay circuit or an output of said third digital delay circuit as an input to said circuit means for providing a positioned clock signal.
Claim 5
Dependent Claim
20 words
A data processing system, according to claim 3, wherein said third time duration is equal to said second time duration.
Claim 6
Dependent Claim
56 words
A data processing system, according to claim 3, wherein said digital clock pulse positioning circuit further comprises: control signal means connected to said selection circuit for controlling selection of said output of said second digital delay circuit or said third digital delay circuit, said control signal means responsive to characteristics of circuits in said IOCC unit.
Claim 7
Dependent Claim
47 words
A data processing system, according to claim 1, wherein time duration for said first and second digital delay circuits are determined by the following relationship: T2 equals 1.5 times a predetermined minimum clock pulse width, and T1 equals a predetermined minimum clock active time duration minus T2.
Claim 8
Dependent Claim
125 words
An input/output control unit comprising: a storage array and a digital clock positioning circuit to position clock signals output from said digital clock pulse positioning circuit to be active when information inputs to said array are stable; wherein said digital clock pulse positioning circuit further comprises: a first digital delay circuit for delaying an input signal by a first time duration T1; a second digital delay circuit responsive to an output of said first digital delay circuit for delaying a signal input to said second digital delay circuit by a second time duration T2; and circuit means responsive to an output of said first digital delay circuit and an output of said second digital delay circuit for providing a positioned clock signal for said array.
Claim 9
Dependent Claim
125 words
An input/output control unit comprising: a storage array and a digital clock positioning circuit to position clock signals output from said digital clock pulse positioning circuit to be active when information inputs to said array are stable; wherein said digital clock pulse positioning circuit further comprises: a first digital delay circuit for delaying an input signal by a first time duration T1; a second digital delay circuit responsive to an output of said first digital delay circuit for delaying a signal input to said second digital delay circuit by a second time duration T2; and circuit means responsive to an output of said first digital delay circuit and an output of said second digital delay circuit for providing a positioned clock signal for said array.
Claim 10
Dependent Claim
31 words
An input/output control unit, according to claim 7, further comprising circuit means for selecting one of a plurality of clock signals as an input to said digital clock pulse positioning circuit.
Claim 11
Dependent Claim
84 words
An input/output control unit, according to claim 7, wherein said digital clock pulse positioning circuit further comprises: a third digital delay circuit responsive to an output of said second digital delay circuit for delaying a signal input to said third digital delay circuit by a third time duration; and a selection circuit for selecting an output of said second digital delay circuit or an output of said third digital delay circuit as an input to said circuit means for providing a positioned clock signal.
Claim 12
Dependent Claim
20 words
An input/output control unit, according to claim 9, wherein said third time duration is equal to said second time duration.
Claim 13
Dependent Claim
56 words
An input/output control unit, according to claim 9, wherein said digital clock pulse positioning circuit further comprising: control signal means connected to said selection circuit for controlling selection of said output of said second digital delay circuit where said third digital delay circuit, said control signal means resonsive to characteristics of circuits in said IOCC unit.
Claim 14
Dependent Claim
47 words
An input/output control unit, according to claim 7, wherein time duration for said first and second digital delay circuits are determined by the following relationship: T2 equals 1.5 times a predetermined minimum clock pulse width, and T1 equals a predetermined minimum clock active time duration minus T2.
References Cited (Backward Citations)
US3941989A
Cited
US4802120A
Cited
US4899273A
Cited
US4797552A
Cited
US5305452A
Cited
US5008636A
Cited
US5233615A
Cited
US5367204A
Cited
US5396598A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-20 | 2000-02-19 | 2000-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-20 | 2004-02-19 | 2004-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-20 | 2008-02-19 | 2008-08-20 | $7700.00 | Window Closed / Lapsed |