Data fusion neural network

Claim 2

Apparatus for forming a fast optimal or near optimal association based on satisfying global constraints expressed in an association matrix, comprising: means including a state memory for storing signals representative of neuron values x i by addresses corresponding to row and column indexes of the association matrix; means including an active list memory for storing signals representative of a list of all active neurons that contribute to the formation of a change Δx i in the neuron value signals stored in the state memory; means for processing the signals representative of active neurons to approximate trajectories representing an evolution of neuron states at discrete intervals of time Δt to obtain signals representative of the change Δx i in the neurons at said intervals; means for replacing the neuron value signals stored in the state memory by signals representative of x i +Δx i ; means for writing the row and column address of x i into the active list memory for a next iteration, if any Δx i is less than zero; means for replacing all neuron value signals corresponding to active neurons stored in the active list by a signal representative of 1.0 if, after any iteration, ΔX i is zero or greater.

Claim 3

Apparatus as claimed in claim 1, wherein the processing means comprises: means for addressing a memory location where a neuron value signal x i is stored by row and column indices j and m in order to sequentially process the neuron value signals one at a time; first signal transform means for transforming the signal representative of neuron value x i into a signal representative of an operator H(x i ); row and column sum accumulation means including row and column sum memories for accumulating the sums ROW j SUM, COL m SUM, and H(x i ) for each active neuron during an iteration; second signal transform means for transforming signal values representative of x i into signals representative of kG(x i ); first signal combining means for combining the ROW j SUM, COL m SUM, and H(x i ) signals to form signals representative of (ROW j SUM-H(x i )) and (COL m SUM-H(x i )); second signal combining means for combining signals representative of constant values c and d with the signals representative of (ROW j SUM-H(x i ) and (COL m SUM-H(x i )) to from signals representative of the differences (ROW j SUM-H(x i )-c) and (COL m SUM-H(x i )-d); third signal transform means for transforming the (ROW j SUM-H(x i )-c) and (COL m SUM-H(x i )-d) into signals representative of an operator F(ROW j SUM-H(x i )-c) and F(COL m SUM-H(x i )-d); third signal combining means for combining the F(ROW j SUM-H(x i )-c) and F(COL m SUM-H(x i )-d) signals with a constant signal b to obtain a signal representative of b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d); fourth signal combining means for combining the signal representative of b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d) with the signal representative of kG(x i ) to obtain a signal representative of kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)); fifth signal combining means for combining the signal representative of kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)) with a constant signal a and with a current neuron value signal x i to form a signal representative of -x i -a+kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)); and sixth signal combining means for combining the signal representative of -x i -a +kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)) with a constant signal Δt to form a signal representative of Δt(-x i -a+kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d))), the signal representative of Δt(-x i -a+kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d))) also representing Δx i .

Claim 4

Apparatus as claimed in claim 2, wherein said first signal transform means includes a look-up table.

Claim 5

Apparatus as claimed in claim 2, wherein operators H, G, and F are identified in the state equation dx i /dt=-x i -a+kG(x i )(b-F(ΣH(x i )-c)-F(ΣH(x m )-d)); jεR i '; mεC i ', and where R i ' is a set of indexes corresponding to inputs to the ith neuron from the same row as the ith neuron, not including the ith neuron, and C i ' is the set of indexes input to the ith neuron from the same column as the ith neuron, not including the ith neuron.

Claim 6

Apparatus as claimed in claim 2, wherein said row and column sum accumulation means includes adder circuits having respective inputs connected to outputs of the first signal transform means and the row and column sum memories, and respective outputs connected to inputs of the row and column sum memories.

Claim 7

Apparatus as claimed in claim 2, wherein said first signal combining means includes subtractor circuits having inputs connected respectively to the outputs of the row and column sum memories and the first signal transform means.

Claim 8

Apparatus as claimed in claim 6, wherein the second signal combining means includes: (1) said subtractor circuits and means including first switches for switching between sources of said constant signals c and d and said output of the first signal transform means; and (2) means including second switches for switching the inputs connected to the row and column sum memory outputs between respective outputs of the subtractor circuits and the row and column sum memory outputs.

Claim 9

Apparatus as claimed in claim 2, wherein said third signal combining means includes a subtractor circuit and means for switching one input of the subtractor circuit between a source of a constant signal b and an output of the subtractor circuit, a second input of the subtractor circuit being connected to the third signal transform means.

Claim 10

Apparatus as claimed in claim 2, wherein said fourth signal combining means includes a multiplier circuit having respective inputs connected to outputs of the third signal combining means and the second signal transform means.

Claim 11

Apparatus as claimed in claim 2, wherein said fifth signal combining means includes an adder circuit and means for switching a first input of the adder circuit between a source of a constant signal a and an output of the fourth signal combining means, and a second input connected to the output of the state memory through temporary register means for delaying a current neuron value signal x i by an amount sufficient to obtain an output from the fourth signal combining means.

Claim 12

Apparatus as claimed in claim 10, wherein the sixth signal combining means includes a first input connected to an output of the adder circuit, a second input connected to the output of the fourth signal combining means, and an output connected to an input of the fourth signal combining means through means for switching between an output of the third signal combining means and an output of the sixth signal combining means.

Claim 13

Apparatus as claimed in claim 11, wherein an input of the state memory is connected to an output of the adder circuit, and further comprising a comparator circuit having a first input connected to an output of the fourth signal combining means; a second input connected to a constant signal source representative of zero; and means connected to the state memory for supplying a non-convergence signal to the state memory when Δx i is less than zero, said non-convergence signal causing the state memory to input a new neuron value x+Δx i from the adder circuit for use in a next iteration.

Claim 14

Apparatus as claimed in claim 1, further comprising temporary register means for starting a row and column address for an active neuron and means for comparing respective outputs of the first and second signal transform means with zero and, if either signal transform means output is greater than zero, rewriting the stored row and column address to the active list memory using an address n provided by a rewrite counter.

Claim 15

Apparatus as claimed in claim 1, further comprising indexing means including an index counter and a rewrite counter connected to an input of the active list memory and to an i limit register, and means for replacing an i limit stored in the i limit register by a maximum count n in the rewrite counter after a last neuron is processed for each iteration, whereby the active list continually grows shorter until convergence is detected.

Claim 18

A method as claimed in claim 15, wherein the processing means comprises: d1. indexing the x i signals by row and column indices j and m in order to sequentially process the x i signals one at a time; d2. transforming a current x i signal into a signal representative of an operator H(x i ); d3. accumulating signals representative of H(x i ) to form signals representative of the sums ROW j SUM and COL m SUM of H(x i ) for each active neuron during an iteration; d4. transforming x i into a signal kG(x i ); d5. combining the ROW j SUM, COL m SUM, and H(x i ) signals to form signals representative of (ROW j SUM-H(x i )) and (COL m SUM-H(x i )); d6. combining signals representative of constant values c and d with the signals representative of (ROW j SUM-H(x i )) and (COL m SUM-H(x i )) to form signals representative of the differences (ROW j SUM-H(x i )-c) and (COL m SUM -H(x i )-d); d7. transforming the (ROW j SUM-H(x i )-c) and (COL m SUM-H(x i )-d) into signals representative of an operator F(ROW j SUM-H(x i )-c) and F(COL m SUM-H(x i )-d); d8. combining the F(ROW j SUM-H(x i )-c) and F(COL m SUM-H(x i )-d) signals with a constant signal b to obtain a signal representative of b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d); d9. combining the signal representative of b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d) with the signal representative of kG(x i ) to obtain a signal representative of kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)); d10. combining the signal representative of kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)) with a constant signal a and with a current neuron value signal x i to form a signal representative of -x i -a+kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)); and d11. combining the signal representative of -x i -a+kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)) with a constant signal Δt to form a signal representative of Δt(-x i -a+kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d))), wherein the signal representative of Δt(-x i -a+kG(x i )(b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d))) also represents Δx i .

Claim 19

A method as claimed in claim 16, wherein steps d2, d4, and d7 respectively comprise the steps of inputting the xi signals to look-up tables.

Claim 20

A method as claimed in claim 16, wherein operators H, G, and F and threshold value e are defined by the state equations dx i /dt=-x i -a+kG(x i )(b-F(ΣH(x i )-c)-F(ΣH(x m )-d)); jεR i '; mεC i ', and where R i ' is a set of indexes corresponding to inputs to the ith neuron from the same row as the ith neuron, not including the ith neuron itself, and C i ' is the set of indexes input to an ith neuron from the same row as the ith neuron, not including the ith neuron itself.

Claim 21

A method as claimed in claim 16, wherein step d3 comprises the step of adding together Successive H(x i ) signals and writing a sum of the successive H(x i ) signals into a row sum memory for each active neuron in a row and into a column sum memory for each active neuron in a column.

Claim 22

A method as claimed in claim 16, wherein step d5 comprises the step of retrieving the ROW j SUM and COL m SUM signals from respective row and column sum memories and combining them with the H(x i ) signal by means of subtractor circuits.

Claim 23

A method as claimed in claim 20, wherein step d6 comprises the step of combining the (ROW j SUM), (COL m SUM), c, and d signals by means of said subtractor circuits, said combining step comprising the steps of operating first switches to switch inputs of the subtractor circuits between sources of said constant signals c and d and said H(x i ) signal, and then operating second switches to switch inputs of the subtractor circuits which are connected to outputs of the row and column sum memories between respective outputs of the subtractor circuits and the row and column sum memory outputs.

Claim 24

A method as claimed in claim 16, wherein step d8 comprises the step of operating a switch to switch an input of a subtractor circuit between a source of a constant signal b and an output of the subtractor circuit, and inputting the signals representative of F(ROW j SUM-H(x i )-c)and F(COL m SUM-H(x i )-d) to a second input of the subtractor circuit.

Claim 25

A method-as claimed in claim 16, wherein step d9 comprises the step of combining the (b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)) and kG(x i ) signals by means of a multiplier circuit.

Claim 26

A method as claimed in claim 23, wherein step d 10 comprises the steps of switching a first input of an adder circuit between a source of a constant signal a and an output of the multiplier circuit, and retrieving a current neuron value signal from the state memory through a temporary register which delays the current neuron value signal xi by an amount sufficient to obtain an output from the multiplier.

Claim 27

A method as claimed in claim 24, wherein step d11 comprises the step of switching a first input of the multiplier circuit from a source of the -x i -a+kG (x i ) (b-F(ROW j SUM-H(x i )-c)-F(COL m SUM-H(x i )-d)) signal to a source of a signal Δt which represents an interval of time at which values of Δx i are captured, to obtain a signal representative of Δx i .

Claim 28

A method as claimed in claim 15, wherein step f comprises the steps of writing x+Δx i into the state memory after comparing the Δx i signal with zero.

Claim 29

A method as claimed in claim 15, further comprising the steps of temporarily starting a row and column address for an active neuron and comparing the respective H(x i ) and G(x i ) signals with zero and, if either H(x i ) or G(x i ) is greater than zero, rewriting the stored row and column address to the active list memory using an address n provided by a rewrite counter.

Claim 30

A method as claimed in claim 15, further comprising the step of replacing an i limit stored in an i limit register by a maximum count n in a rewrite counter after a last neuron is processed for each iteration, whereby the active list continually grows shorter until convergence is detected.