DS/CDMA receiver using moving-averaged pilot signals for weighting and phase rotation of orthogonal data symbol vectors

Claim 2

A direct sequence spread spectrum receiver comprising: first correlator means multiplying in-phase and quadrature spread data signals and in-phase and quadrature spread pilot signals with orthogonal despreading sequences at a chip rate to produce in-phase and quadrature orthogonal despread data signals and in-phase and quadrature despread pilot signals; data integrator means integrating the in-phase and quadrature despread data signals at a symbol rate to produce in-phase and quadrature data symbols; pilot integrator means integrating the in-phase and quadrature despread pilot signals at said symbol rate to produce in-phase and quadrature pilot symbols; first and second moving average means successively summing a predetermined number of the in-phase and quadrature pilot symbols to produce first and second moving average values, respectively; first and second multiplier means multiplying the in-phase and quadrature data symbols of the data integrator means with the first and second moving average values, respectively; and means summing output signals of the first and second multiplier means.

Claim 3

A direct sequence spread spectrum receiver as claimed in claim 1, further comprising: first delay means introducing a delay to the in-phase data symbol of said data integrator by an amount corresponding to one half of a predetermined number of in-phase pilot symbols and applying the delayed symbol to said first multiplier means; and second delay means introducing a delay to the quadrature data symbol of said data integrator by an amount corresponding to one half of a predetermined number of quadrature pilot symbols and applying the delayed symbol to said second multiplier means.

Claim 4

A direct sequence spread spectrum receiver as claimed in claim 1, further comprising a sync acquisition and tracking circuit comprising: register means storing a plurality of phase position signals; first selector means for cyclically selecting each one of said phase position signals in response to a shift command signal; a pseudo-random number (PN) generator for producing two orthogonal PN sequences in accordance with the selected phase position signals; second correlator means multiplying the in-phase and quadrature spread pilot signals with the PN sequences of the PN generator at said chip rate to produce in-phase and quadrature despread pilot signals and integrating the in-phase and quadrature despread pilot signals at predetermined intervals to produce a correlation value; a plurality of accumulator means; second selector means cyclically selecting each one of said accumulator means in response to said shift command signal and applying the correlation value to the selected accumulator means to thereby cause same to produce a total sum of the correlation values which are produced by said second correlator means while said phase position signals are being cyclically selected and applied to said PN sequence generator; and control means connected to said accumulator means for generating said shift command signal at a predetermined rate, selecting the highest total sum of the correlation value from the total sums of all of said accumulator means, selecting the phase position signal which corresponds to the selected total sum, generating orthogonal despreading sequences corresponding to the selected phase position signal, and applying the orthogonal despreading sequences to said first correlator means.

Claim 5

A direct sequence spread spectrum receiver as claimed in claim 3, further comprising means for storing therein a plurality of different sets of phase position signals and loading each one of said sets of phase position signals therefrom into said register means when all of said accumulator means produce said total sums of correlation values for a set of phase position signals currently stored in said register means.

Claim 6

A direct sequence spread spectrum receiver as claimed in claim 3, wherein said predetermined rate at which said shift command signal is generated is higher than a rate at which Rayleigh fading occurs.

Claim 7

A direct sequence spread spectrum receiver as claimed in claim 5, wherein said predetermined rate at which said shift command signal is generated corresponds to an interval not exceeding π/2 radian notation of said in-phase and quadrature pilot signals.

Claim 8

A direct sequence spread spectrum receiver comprising: a plurality of demodulators; and an adder connected to outputs of said demodulators, each of said demodulators comprising: first correlator means multiplying in-phase and quadrature spread data signals and in-phase and quadrature spread pilot signals with orthogonal despreading sequences at a chip rate to produce in-phase and quadrature despread data signals and in-phase and quadrature despread pilot signals; data integrator means integrating the in-phase and quadrature despread data signals at a symbol rate to produce in-phase and quadrature data symbols; pilot integrator means integrating the in-phase and quadrature despread pilot signals at said symbol rate to produce in-phase and quadrature pilot symbols; first and second moving average means successively summing a predetermined number of the in-phase and quadrature pilot symbols to produce first and second moving average values, respectively; first and second multiplier means multiplying the in-phase and quadrature data symbols of the data integrator means with the first and second moving average values, respectively; and means summing output signals of the first and second multiplier means to produce a sum signal and supplying the sum signal to said adder.

Claim 9

A direct sequence spread spectrum receiver comprising: a plurality of demodulators; and an adder connected to outputs of said demodulators, each of said demodulators comprising: first correlator means multiplying in-phase and quadrature spread data signals and in-phase and quadrature spread pilot signals with orthogonal despreading sequences at a chip rate to produce in-phase and quadrature despread data signals and in-phase and quadrature despread pilot signals; data integrator means integrating the in-phase and quadrature despread data signals at a symbol rate to produce in-phase and quadrature data symbols; pilot integrator means integrating the in-phase and quadrature despread pilot signals at said symbol rate to produce in-phase and quadrature pilot symbols; first and second moving average means successively summing a predetermined number of the in-phase and quadrature pilot symbols to produce first and second moving average values, respectively; first and second multiplier means multiplying the in-phase and quadrature data symbols of the data integrator means with the first and second moving average values, respectively; and means summing output signals of the first and second multiplier means to produce a sum signal and supplying the sum signal to said adder.

Claim 10

A direct sequence spread spectrum receiver as claimed in claim 7, each of said demodulators further comprising: first delay means introducing a delay to the in-phase data symbol of said data integrator by an amount corresponding to one half of a predetermined number of in-phase pilot symbols and applying the delayed symbol to said first multiplier means; and second delay means introducing a delay to the quadrature data symbol of said data integrator by an amount corresponding to one half of a predetermined number of quadrature pilot symbols and applying the delayed symbol to said second multiplier means.

Claim 11

A direct sequence spread spectrum receiver as claimed in claim 7, further comprising a sync acquisition and tracking circuit comprising: register means storing a plurality of phase position signals; first selector means for cyclically selecting each one of said phase position signals in response to a shift command signal; a pseudo-random number (PN) generator for producing orthogonal PN sequences in accordance with the selected phase position signal; second correlator means multiplying the in-phase and quadrature spread pilot signals with the orthogonal PN sequences of the PN generator at said chip rate to produce in-phase and quadrature despread pilot signals and integrating the in-phase and quadrature despread pilot signals at predetermined intervals to produce a correlation value; a plurality of accumulator means; second selector means cyclically selecting each one of said accumulator means in response to said shift command signal and applying the correlation value to the selected accumulator means to thereby cause same to produce a total sum of the correlation values which are produced by said second correlator means while said phase position signals are being cyclically selected and applied to said PN sequence generator; and control means connected to said accumulator means for generating said shift command signal at a predetermined rate, selecting the highest total sums of correlation values from the total sums of all of said accumulator means, selecting ones of said phase position signals which correspond to the selected total sums, generating a plurality of pairs of orthogonal despreading sequences corresponding to the selected phase position signals, and applying the plurality of pairs of orthogonal despreading sequences to said demodulators, one pair to each demodulator.

Claim 12

A direct sequence spread spectrum receiver as claimed in claim 7, further comprising means for storing therein a plurality of different sets of phase position signals and loading each one of said sets of phase position signals therefrom into said register means when all of said accumulator means produce said total sums of correlation values for a set of phase position signals currently stored in said register means.

Claim 13

A direct sequence spread spectrum receiver as claimed in claim 7, wherein said predetermined rate at which said shift command signal is generated is higher than a rate at which Rayleigh fading occurs.

Claim 14

A direct sequence spread spectrum receiver as claimed in claim 11, wherein said predetermined rate at which said shift command signal is generated corresponds to an interval not exceeding π/2 radian rotation of said in-phase and quadrature pilot signals.

Claim 15

A direct sequence spread spectrum receiver as claimed in claim 2, further comprising a sync acquisition and tracking circuit comprising: register means storing a plurality of phase position signals; first selector means cyclically selecting each one of said phase position signals in response to a shift command signal; a pseudo-random number (PN) generator for producing two orthogonal PN sequences in accordance with the selected phase position signal; second correlator means multiplying the in-phase and quadrature spread pilot signals with the PN sequences of the PN generator at said chip rate to produce in-phase and quadrature despread pilot signals and integrating the in-phase and quadrature despread pilot signals at predetermined intervals to produce a correlation value; a plurality of accumulator means; second selector means cyclically selecting each one of said accumulator means in response to said shift command signal and applying the correlation value to the selected accumulator means to thereby cause same to produce a total sum of the correlation values which are produced by said second correlator means while said phase position signals are being cyclically selected and applied to said PN sequence generator; and control means connected to said accumulator means for generating said shift command signal at a predetermined rate, selecting the highest total sum of the correlation value from the total sums of all of said accumulator means, selecting the phase position signal which corresponds to the selected total sum, generating orthogonal despreading sequences corresponding to the selected phase position signal, and applying the orthogonal despreading sequences to said first correlator means.

Claim 16

A direct sequence spread spectrum receiver as claimed in claim 8, further comprising a sync acquisition and tracking circuit comprising: register means storing a plurality of phase position signals; first selector means cyclically selecting each one of said phase position signals in response to a shift command signal; a pseudo-random number (PN) generator for producing orthogonal PN sequences in accordance with the selected phase position signal; correlator means multiplying the in-phase and quadrature spread pilot signals with the orthogonal PN sequences of the PN generator at said chip rate to produce in-phase and quadrature despread pilot signals and integrating the in-phase and quadrature despread pilot signals at predetermined intervals to produce a correlation value; a plurality of accumulator means; second selector means cyclically selecting each one of said accumulator means in response to said shift command signal and applying the correlation value to the selected accumulator means to thereby cause same to produce a total sum of the correlation values which are produced by said correlator means while said phase position signals are being cyclically selected and applied to said PN sequence generator; and control means connected to said accumulator means for generating said shift command signal at a predetermined rate, selecting the highest total sums of correlation values from the total sums of all of said accumulator means, selecting ones of said phase position signals which correspond to the selected total sums, generating a plurality of pairs of orthogonal despreading sequences corresponding to the selected phase position signals, and applying the plurality of pairs of orthogonal despreading sequences to said demodulators, one pair to each demodulator.

Claim 17

A direct sequence spread spectrum receiver comprising: correlator for multiplying in-phase and quadrature spread data signals and in-phase and quadrature spread pilot signals with orthogonal despreading sequences at a chip rate to produce in-phase and quadrature orthogonal despread data signals and in-phase and quadrature despread pilot signals; data integrator for integrating the in-phase and quadrature despread data signals at a symbol rate to produce in-phase and quadrature data symbols; pilot integrator for integrating the in-phase and quadrature despread pilot signals at said symbol rate to produce in-phase and quadrature pilot symbols; first and second moving average circuits for successively summing a predetermined number of the in-phase and quadrature pilot symbols to produce first and second moving average values, respectively; first and second multipliers for multiplying the in-phase and quadrature data symbols of the data integrator with the first and second moving average values, respectively; and adder summing output signals of the first and second multipliers.

Claim 18

A direct sequence spread spectrum receiver comprising: correlator for multiplying in-phase and quadrature spread data signals and in-phase and quadrature spread pilot signals with orthogonal despreading sequences at a chip rate to produce in-phase and quadrature orthogonal despread data signals and in-phase and quadrature despread pilot signals; data integrator for integrating the in-phase and quadrature despread data signals at a symbol rate to produce in-phase and quadrature data symbols; pilot integrator for integrating the in-phase and quadrature despread pilot signals at said symbol rate to produce in-phase and quadrature pilot symbols; first and second moving average circuits for successively summing a predetermined number of the in-phase and quadrature pilot symbols to produce first and second moving average values, respectively; first and second multipliers for multiplying the in-phase and quadrature data symbols of the data integrator with the first and second moving average values, respectively; and adder summing output signals of the first and second multipliers.

Claim 19

A direct sequence spread spectrum receiver comprising: a plurality of demodulators; and a first adder connected to outputs of said demodulators, each of said demodulators comprising: correlator for multiplying in-phase and quadrature spread data signals and in-phase and quadrature spread pilot signals with orthogonal despreading sequences at a chip rate to produce in-phase and quadrature despread data signals and in-phase and quadrature despread pilot signals; data integrator for integrating the in-phase and quadrature despread data signals at a symbol rate to produce in-phase and quadrature data symbols; pilot integrator for integrating the in-phase and quadrature despread pilot signals at said symbol rate to produce in-phase and quadrature pilot symbols; first and second moving average circuits for successively summing a predetermined number of the in-phase and quadrature pilot symbols to produce first and second moving average values, respectively; first and second multipliers for multiplying the in-phase and quadrature data symbols of the data integrator with the first and second moving average values, respectively; and second adder for summing output signals of the first and second multipliers to produce a sum signal and supplying the sum signal to a first adder.

Claim 20

A direct sequence spread spectrum receiver comprising: a plurality of demodulators; and a first adder connected to outputs of said demodulators, each of said demodulators comprising: correlator for multiplying in-phase and quadrature spread data signals and in-phase and quadrature spread pilot signals with orthogonal despreading sequences at a chip rate to produce in-phase and quadrature despread data signals and in-phase and quadrature despread pilot signals; data integrator for integrating the in-phase and quadrature despread data signals at a symbol rate to produce in-phase and quadrature data symbols; pilot integrator for integrating the in-phase and quadrature despread pilot signals at said symbol rate to produce in-phase and quadrature pilot symbols; first and second moving average circuits for successively summing a predetermined number of the in-phase and quadrature pilot symbols to produce first and second moving average values, respectively; first and second multipliers for multiplying the in-phase and quadrature data symbols of the data integrator with the first and second moving average values, respectively; and second adder for summing output signals of the first and second multipliers to produce a sum signal and supplying the sum signal to a first adder.