US5093841A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock acquisition in a spread spectrum system
Assignee: Verizon Patent and Licensing Inc
•
Filing: 1990-01-30
•
Granted: 1992-03-03
•
Expires: 2010-01-30
Abstract
Abstract A circuit and method is disclosed for recovering the transmitter clock at a receiver in a direct sequence spread spectrum communication system where a transmitter and receiver run independent clocks of nominally the same frequency. At the receiver, to select the phase of the local clock that yields the strongest signal, a clock recovery circuitry cycles through M phases of the locally generated receiver clock. The cycling is halted and the phase is locked soon as an indication is obtained that a phase is valid. Alternatively, all M phases of the local clock are tested for validity or invalidity, and depending on the resulting pattern of valid and invalid phases, a particular phase is selected for the local clock. A phase is valid or invalid depending on whether there is a second correlation crossing at the expected instant one data bit period after a first correlation crossing.
Inventors
- 👤 Jan P. Vancraeynest
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:56
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04B; H04B1/00; H04B1/69; H04B1/707
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
155 words
A method for synchronizing a local receiver clock with a transmitter clock, said receiver clock being located at a receiver which receives a transmitted digital data bit stream in a spread spectrum format wherein each data bit comprises N chips, wherein N is an integer greater than one, said method comprising the steps of: at said receiver, cycling through a plurality of phases of said local receiver clock, and for each of said phases determining whether the phase is valid and the local receiver clock and transmitter clock are synchronized by determining if a correlation threshold crossing of a second data bit of said data bit stream is detected at said receiver at an unexpected instant N chip time periods after a correlation threshold crossing of a first data bit is detected, and halting said cycling and locking the phase of said local receiver clock when one of said phases is determined as being valid.
Claim 2
Independent Claim
155 words
A method for synchronizing a local receiver clock with a transmitter clock, said receiver clock being located at a receiver which receives a transmitted digital data bit stream in a spread spectrum format wherein each data bit comprises N chips, wherein N is an integer greater than one, said method comprising the steps of: at said receiver, cycling through a plurality of phases of said local receiver clock, and for each of said phases determining whether the phase is valid and the local receiver clock and transmitter clock are synchronized by determining if a correlation threshold crossing of a second data bit of said data bit stream is detected at said receiver at an unexpected instant N chip time periods after a correlation threshold crossing of a first data bit is detected, and halting said cycling and locking the phase of said local receiver clock when one of said phases is determined as being valid.
Claim 3
Independent Claim
192 words
A method for synchronizing a local receiver clock with a transmitter clock, said receiver clock being located at a receiver which receives a transmitted digital data bit stream, said method comprising the steps of: at said receiver, cycling through a plurality of phases of said local receiver clock, and for each of said phases determining whether the phase is valid and the local receiver clock and transmitter clock are synchronized by determining if a second data bit of said data bit stream is detected a predetermined time interval after a first data bit is detected, and halting said cycling and locking the phase of said local receiver clock when one of said phases is determined as being valid, wherein said receiver receives a signal in a spread spectrum format comprising N chips per data bit, where N is an integer greater than 1, and wherein the step of determining if one of said phases is valid has a duration of 2N chip time periods and comprises determining if a correlation threshold crossing of the second data bit occurs N chip time periods after a correlation threshold crossing of the first data bit.
Claim 4
Independent Claim
192 words
A method for synchronizing a local receiver clock with a transmitter clock, said receiver clock being located at a receiver which receives a transmitted digital data bit stream, said method comprising the steps of: at said receiver, cycling through a plurality of phases of said local receiver clock, and for each of said phases determining whether the phase is valid and the local receiver clock and transmitter clock are synchronized by determining if a second data bit of said data bit stream is detected a predetermined time interval after a first data bit is detected, and halting said cycling and locking the phase of said local receiver clock when one of said phases is determined as being valid, wherein said receiver receives a signal in a spread spectrum format comprising N chips per data bit, where N is an integer greater than 1, and wherein the step of determining if one of said phases is valid has a duration of 2N chip time periods and comprises determining if a correlation threshold crossing of the second data bit occurs N chip time periods after a correlation threshold crossing of the first data bit.
Claim 5
Dependent Claim
34 words
The method of claim 2 wherein said plurality of phases comprises M phases, wherein M is an integer greater than one, and wherein said cycling step lasts a maximum of 2MN chip time periods.
Claim 6
Dependent Claim
28 words
The method of claim 3 wherein said signal in spread spectrum format comprises data packets and wherein each packet has a preamble of at least 2M data bits.
Claim 7
Dependent Claim
18 words
The method of claim 4 wherein said synchronizing method is carried out no more than once per packet.
Claim 8
Dependent Claim
29 words
The method of claim 2 wherein said method further comprises resuming said cycling and determining steps if after a certain time period said one phase is no longer valid.
Claim 9
Independent Claim
163 words
A method for recovering a local clock at a receiver which receives a digital signal in spread spectrum format, wherein said signal comprises N chips per data bit, where N is an integer greater than one, said method comprising, cycling through M phases of said local clock, where M is an integer greater than one, at a rate which is at most one-half a bit rate of said signal, for each of said phases, determining if the phase is valid by determining if a correlation threshold crossing of a second data bit of said signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit is detected at said receiver, and halting said cycling step and locking the phase of said local clock at a particular one of said M phases in response to said determining step, when it is determined that a particular one of said phases is valid.
Claim 10
Independent Claim
163 words
A method for recovering a local clock at a receiver which receives a digital signal in spread spectrum format, wherein said signal comprises N chips per data bit, where N is an integer greater than one, said method comprising, cycling through M phases of said local clock, where M is an integer greater than one, at a rate which is at most one-half a bit rate of said signal, for each of said phases, determining if the phase is valid by determining if a correlation threshold crossing of a second data bit of said signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit is detected at said receiver, and halting said cycling step and locking the phase of said local clock at a particular one of said M phases in response to said determining step, when it is determined that a particular one of said phases is valid.
Claim 11
Dependent Claim
151 words
A circuit forming part of a receiver for synchronizing a local receiver clock with a transmitter clock, said receiver receiving a digital signal in spread spectrum format wherein each bit comprises N chips, where N is an integer greater than one, said circuit comprising: means for cycling through a plurality of phases of said local receiver clock at a rate which is at most one-half a bit rate of the digital signal received at said receiver, means for determining if each of said phases is valid by determining if a correlation threshold crossing of a second data bit of said signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit of said signal is detected, and means for locking the phase of said local receiver clock when said determining means indicates one of said phases is valid.
Claim 12
Dependent Claim
151 words
A circuit forming part of a receiver for synchronizing a local receiver clock with a transmitter clock, said receiver receiving a digital signal in spread spectrum format wherein each bit comprises N chips, where N is an integer greater than one, said circuit comprising: means for cycling through a plurality of phases of said local receiver clock at a rate which is at most one-half a bit rate of the digital signal received at said receiver, means for determining if each of said phases is valid by determining if a correlation threshold crossing of a second data bit of said signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit of said signal is detected, and means for locking the phase of said local receiver clock when said determining means indicates one of said phases is valid.
Claim 13
Dependent Claim
148 words
A clock recovery circuit for synchronizing a local clock at a receiver with a digital signal in spread spectrum format, wherein said signal comprises N chips per data bit, where N is an integer greater than one, said circuit comprising: means for cycling through M phases of said local receiver clock, where M is an integer greater than one, at a rate which is at most one-half a bit rate of said signal, means for determining if each of said phases is valid by determining if a correlation threshold crossing of a second data bit of said signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit is detected at said receiver, and means for locking the phase of said local receiver clock when said determining means indicates one of said phases is valid.
Claim 14
Dependent Claim
148 words
A clock recovery circuit for synchronizing a local clock at a receiver with a digital signal in spread spectrum format, wherein said signal comprises N chips per data bit, where N is an integer greater than one, said circuit comprising: means for cycling through M phases of said local receiver clock, where M is an integer greater than one, at a rate which is at most one-half a bit rate of said signal, means for determining if each of said phases is valid by determining if a correlation threshold crossing of a second data bit of said signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit is detected at said receiver, and means for locking the phase of said local receiver clock when said determining means indicates one of said phases is valid.
Claim 15
Dependent Claim
65 words
The circuit of claim 9 wherein said cycling means comprises means for generating a periodic signal having the same nominal frequency as said spread spectrum signal, a delay network for deriving a plurality of phases of said periodic signal to form said plurality of phases of said local receiver clock, and multiplexer means for sequentially selecting particular ones of said phases of said local clock.
Claim 16
Dependent Claim
199 words
A clock recovery circuit for synchronizing a local clock at a receiver with a signal in spread spectrum format, wherein said signal comprises N chips per data bit, where N is an integer greater than one, said circuit comprising: means for cycling through M phases of said local receiver clock, where M is an integer greater than one, means for determining if each of said phases is valid by determining if a correlation threshold crossing of a second data bit is detected at said receiver N chip time periods after a correlation threshold crossing of a first data bit is detected at said receiver, and means for locking the phase of said local receiver clock when said determining means indicates one of said phases is valid, wherein said determining means comprises first circuit means for asserting a first signal N chip periods after said first data bit is detected, and second circuit means for asserting a second, clock detect signal when said second data bit is detected N chip periods after said first data bit is detected, said second circuit means asserting said second signal only when said first signal coincides with the detection of said second data bit.
Claim 17
Dependent Claim
199 words
A clock recovery circuit for synchronizing a local clock at a receiver with a signal in spread spectrum format, wherein said signal comprises N chips per data bit, where N is an integer greater than one, said circuit comprising: means for cycling through M phases of said local receiver clock, where M is an integer greater than one, means for determining if each of said phases is valid by determining if a correlation threshold crossing of a second data bit is detected at said receiver N chip time periods after a correlation threshold crossing of a first data bit is detected at said receiver, and means for locking the phase of said local receiver clock when said determining means indicates one of said phases is valid, wherein said determining means comprises first circuit means for asserting a first signal N chip periods after said first data bit is detected, and second circuit means for asserting a second, clock detect signal when said second data bit is detected N chip periods after said first data bit is detected, said second circuit means asserting said second signal only when said first signal coincides with the detection of said second data bit.
Claim 18
Dependent Claim
31 words
The circuit of claim 11 wherein said locking means comprises third circuit means for locking the phase of said local clock selected by said multiplexer when said second signal is asserted.
Claim 19
Dependent Claim
146 words
A despreader for use in a spread spectrum communication system comprising: a shift register for receiving a signal in spread spectrum format wherein each data bit is encoded by N chips, a correlator for determining at each chip time period of said spread spectrum signal the number of matches between the chips in the shift register and a predetermined reference sequence and for producing a data bit detection signal when the number of matches exceeds or falls below a correlation threshold, means for generating and cycling through a plurality of phases of a local clock, first circuit means for producing an output signal N chip time periods after receiving a first bit detection signal from said correlator, second circuit means for asserting a clock detect signal when a second bit detection signal from said correlator coincides with said output signal of said first circuit means, and
Claim 20
Dependent Claim
146 words
A despreader for use in a spread spectrum communication system comprising: a shift register for receiving a signal in spread spectrum format wherein each data bit is encoded by N chips, a correlator for determining at each chip time period of said spread spectrum signal the number of matches between the chips in the shift register and a predetermined reference sequence and for producing a data bit detection signal when the number of matches exceeds or falls below a correlation threshold, means for generating and cycling through a plurality of phases of a local clock, first circuit means for producing an output signal N chip time periods after receiving a first bit detection signal from said correlator, second circuit means for asserting a clock detect signal when a second bit detection signal from said correlator coincides with said output signal of said first circuit means, and
Claim 21
Independent Claim
153 words
A method for synchronizing a local receiver clock with a transmitter clock, said receiver clock being located at a receiver which receives a transmittal digital data bit stream comprising N chips per data bit where N is an integer greater than one, said method comprising the steps of: generating a plurality of phases of said local receiver clock, determining whether each of said phases is valid or invalid by determining if a correlation threshold crossing of a second data bit of said data bit stream is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit of said data bit stream is detected at said receiver to generate a pattern of valid and invalid phases, and selecting a particular one of said phases based on the pattern of valid or invalid phases and locking the local clock in the selected phase.
Claim 22
Independent Claim
153 words
A method for synchronizing a local receiver clock with a transmitter clock, said receiver clock being located at a receiver which receives a transmittal digital data bit stream comprising N chips per data bit where N is an integer greater than one, said method comprising the steps of: generating a plurality of phases of said local receiver clock, determining whether each of said phases is valid or invalid by determining if a correlation threshold crossing of a second data bit of said data bit stream is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit of said data bit stream is detected at said receiver to generate a pattern of valid and invalid phases, and selecting a particular one of said phases based on the pattern of valid or invalid phases and locking the local clock in the selected phase.
Claim 23
Dependent Claim
26 words
The method of claim 14 wherein said generating step comprises cycling through said phases by switching to the next earlier phase after N chip time periods.
Claim 24
Dependent Claim
26 words
The method of claim 14 wherein said selecting step comprises obtaining said selected phase from a memory depending on the pattern of valid or invalid phases.
Claim 25
Independent Claim
131 words
A method for synchronizing a local clock at a receiver with a signal received at said receiver in spread spectrum format, wherein said signal comprises N chips per data bit, where N is an integer greater than one, said method comprising cycling through phases M of said local receiver clock at a rate which is at most one-half a bit rate of said signal, where M is an integer greater than one, and determining whether each of said phases is valid or invalid by determining whether or not a correlation threshold crossing of a second data bit of said signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit of said signal is detected at said receiver.
Claim 26
Independent Claim
131 words
A method for synchronizing a local clock at a receiver with a signal received at said receiver in spread spectrum format, wherein said signal comprises N chips per data bit, where N is an integer greater than one, said method comprising cycling through phases M of said local receiver clock at a rate which is at most one-half a bit rate of said signal, where M is an integer greater than one, and determining whether each of said phases is valid or invalid by determining whether or not a correlation threshold crossing of a second data bit of said signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit of said signal is detected at said receiver.
Claim 27
Dependent Claim
32 words
The method of claim 17 wherein said method further comprises halting said cycling and locking the phase of the local clock at the first one of said phases determined to be valid.
Claim 28
Dependent Claim
48 words
The method of claim 17 wherein said method further comprises the steps of selecting a particular one of said phases based on the pattern of valid and invalid phases obtained as a result of said cycling and determining steps and locking the local clock in the selected phase.
Claim 29
Dependent Claim
99 words
A circuit forming part of a receiver for synchronizing a local receiver clock with a transmitter clock comprising means for cycling through a plurality of phases o said local receiver clock, and means for determining if a phase is valid or invalid by determining whether or not a correlation threshold of a second data bit of a digital signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit of said digital signal is detected at said receiver, where N is an integer greater than one.
Claim 30
Dependent Claim
99 words
A circuit forming part of a receiver for synchronizing a local receiver clock with a transmitter clock comprising means for cycling through a plurality of phases o said local receiver clock, and means for determining if a phase is valid or invalid by determining whether or not a correlation threshold of a second data bit of a digital signal is detected at said receiver at an expected instant N chip time periods after a correlation threshold crossing of a first data bit of said digital signal is detected at said receiver, where N is an integer greater than one.
Claim 31
Dependent Claim
34 words
The circuit of claim 20 wherein said circuit further comprises means for halting said cycling and locking the phase of said local clock at the first one of said phases determined to be valid.
Claim 32
Dependent Claim
45 words
The circuit of claim 20 wherein said circuit further comprises means for selecting a particular one of said phases based o the pattern of valid and invalid phases produced by said cycling and determining means, and for locking the local clock in the selected phase.
References Cited (Backward Citations)
US3447085A
Cited
US3502976A
Cited
US3742372A
Cited
US3646452A
Cited
US4423517A
Cited
US4475208A
Cited
US4559633A
Cited
US4639932A
Cited
US4774715A
Cited
US4862484A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |