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US5548251A
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High-frequency clock generator using lower frequency voltage controlled ring oscillator
Assignee: Electronics Research and Service Organization
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Filing: 1995-06-23
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Granted: 1996-08-20
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Expires: 2015-06-23
Abstract
Abstract A low noise high-frequency clock generator using a low speed voltage controlled oscillator which includes 2m differential delay elements connected in series in an inverting configuration, where m is an integer greater than 0. The output of the 2mth delay element is coupled to the input of the first delay element in a non-inverting configuration. M 2-input exclusive NOR gates are provided wherein respective input pairs are taken from positive terminal inputs of adjacent delay elements. The clock generator also includes an m-input OR gate coupled to the m-outputs from the respective m exclusive NOR gates for generating the clock generator output signal. The delay elements have a variable delay associated therewith controlled by a control delay signal DCS. Changes in the delay associated with each delay element changes the frequency of the clock generator output signal wherein the output frequency is equal to 1/(2d), where d is the time delay associated with each delay element.
Inventors
- 👤 Shu-Kuang Chou
- 👤 Jiunn-Fu Liou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:22
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/023; H03K3/0231; H03K3/0315; H03K3/0322
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
125 words
A low noise clock generator, comprising: 2m inversion elements connected in series, where m is an integer greater than zero, each inversion element inverting a respective input signal after a preselected delay d, an input of a first one of said 2m inversion elements being coupled to an output of a 2mth inversion element; m comparison means each having first and second inputs, each said first and second inputs being respectively coupled to adjacent inversion elements, each one of said m comparison means having an output for providing a logic one signal when said respective first and second inputs match; and conjunctive logic means responsive to said m comparison means for generating an oscillator output signal having a frequency defined as a function of d.
Claim 2
Dependent Claim
125 words
A low noise clock generator, comprising: 2m inversion elements connected in series, where m is an integer greater than zero, each inversion element inverting a respective input signal after a preselected delay d, an input of a first one of said 2m inversion elements being coupled to an output of a 2mth inversion element; m comparison means each having first and second inputs, each said first and second inputs being respectively coupled to adjacent inversion elements, each one of said m comparison means having an output for providing a logic one signal when said respective first and second inputs match; and conjunctive logic means responsive to said m comparison means for generating an oscillator output signal having a frequency defined as a function of d.
Claim 3
Dependent Claim
18 words
The oscillator of claim 1, wherein at least one of said inversion element comprises a differential delay element.
Claim 4
Dependent Claim
19 words
The oscillator of claim 1 wherein at least one of said m comparison means comprises an exclusive NOR gate.
Claim 5
Dependent Claim
15 words
The oscillator of claim 1 wherein said conjunctive logic means comprises an m-input OR gate.
Claim 6
Dependent Claim
46 words
The oscillator of claim 1 wherein each inversion element is responsive to a voltage control signal for varying said delay d, wherein said delay d is selected as a function of a magnitude of said voltage control signal to thereby vary said oscillator output signal frequency.
Claim 7
Dependent Claim
168 words
A low noise clock generator for generating an output signal having a variable frequency using a control signal, comprising: 2m differential delay elements each coupled to said control signal for inverting a respective input signal and being of the type having a delay d, said delay elements being connected in series in an inverting configuration, an output of a 2mth one of said delay elements being coupled to an input of a first one of said delay elements in a non-inverting configuration, said delay d being variable as a function of a voltage of said control signal; m exclusive NOR gates each having first and second inputs, each one of said m first and second inputs being respectively coupled to adjacent delay elements, each exclusive NOR gate providing a logic one output signal when said respective first and second inputs match; and, an m-input OR gate responsive to said m exclusive NOR gates for generating said generator output signal having a frequency defined as a function of d.
Claim 8
Dependent Claim
168 words
A low noise clock generator for generating an output signal having a variable frequency using a control signal, comprising: 2m differential delay elements each coupled to said control signal for inverting a respective input signal and being of the type having a delay d, said delay elements being connected in series in an inverting configuration, an output of a 2mth one of said delay elements being coupled to an input of a first one of said delay elements in a non-inverting configuration, said delay d being variable as a function of a voltage of said control signal; m exclusive NOR gates each having first and second inputs, each one of said m first and second inputs being respectively coupled to adjacent delay elements, each exclusive NOR gate providing a logic one output signal when said respective first and second inputs match; and, an m-input OR gate responsive to said m exclusive NOR gates for generating said generator output signal having a frequency defined as a function of d.
Claim 9
Dependent Claim
40 words
The generator of claim 6 wherein said generator output signal has a frequency value computed according to the following equation: f.sub.VCO =1/(2*d) where: f VCO =clock generator output frequency value; and, d=a time delay associated with each differential delay element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-08-20 | 2000-02-19 | 2000-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-20 | 2004-02-19 | 2004-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-20 | 2008-02-19 | 2008-08-20 | $7700.00 | Window Closed / Lapsed |