Patent US5548247A successfully refreshed from Google Patents.
US5548247A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier having a field-effect transistor with gate biased at a potential lower than source potential
Assignee: Mitsumi Electric Co Ltd
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Filing: 1994-12-27
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Granted: 1996-08-20
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Expires: 2014-12-27
Abstract
Abstract An amplifier includes: a FET having a source electrode, a drain electrode and a gate electrode, wherein an input signal input to the gate electrode is amplified by the FET and an output signal indicating the amplified input signal is output from the drain electrode; a first voltage biasing unit, coupled to the source electrode of the FET, for biasing the source electrode at a preset positive potential; and a second voltage biasing unit, coupled to the gate electrode of the FET, for biasing the gate electrode at a potential lower than the potential of the source electrode during the operation of the FET.
Inventors
- 👤 Toshikazu Ogino
- 👤 Ryoji Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:21
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/306; H03F3/00; H03F3/189; H03F3/19; H03F3/193; H03F3/1935
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
126 words
An amplifier comprising: a FET having a source electrode, a gate electrode and a drain electrode, wherein an input signal input to the gate electrode is amplified by the FET, and an output signal indicating the amplified input signal is output from the drain electrode; first voltage biasing means, coupled to said source electrode of said FET, for biasing the source electrode at a preset positive potential; and second voltage biasing means, coupled to said gate electrode of said FET, for biasing the gate electrode at a potential lower than the potential of the source electrode during the operation of said FET, wherein said first voltage biasing means comprises a diode having a grounded cathode and an anode coupled to the source electrode of said FET.
Claim 2
Dependent Claim
126 words
An amplifier comprising: a FET having a source electrode, a gate electrode and a drain electrode, wherein an input signal input to the gate electrode is amplified by the FET, and an output signal indicating the amplified input signal is output from the drain electrode; first voltage biasing means, coupled to said source electrode of said FET, for biasing the source electrode at a preset positive potential; and second voltage biasing means, coupled to said gate electrode of said FET, for biasing the gate electrode at a potential lower than the potential of the source electrode during the operation of said FET, wherein said first voltage biasing means comprises a diode having a grounded cathode and an anode coupled to the source electrode of said FET.
Claim 3
Dependent Claim
159 words
An amplifier comprising: a FET having a source electrode, a gate electrode and a drain electrode, wherein an input signal input to the gate electrode is amplified by the FET, and an output signal indicating the amplified input signal is output from the drain electrode; first voltage biasing means, coupled to said source electrode of said FET, for biasing the source electrode at a preset positive potential; and second voltage biasing means, coupled to said gate electrode of said FET, for biasing the gate electrode at a potential lower than the potential of the source electrode during the operation of said FET, wherein said second voltage biasing means comprises: a transistor having an emitter and a collector; a first resistor having one end coupled to a source power terminal and the other end coupled to the emitter of said transistor; and a second resistor having one end coupled to the collector of said transistor and the other end grounded.
Claim 4
Dependent Claim
159 words
An amplifier comprising: a FET having a source electrode, a gate electrode and a drain electrode, wherein an input signal input to the gate electrode is amplified by the FET, and an output signal indicating the amplified input signal is output from the drain electrode; first voltage biasing means, coupled to said source electrode of said FET, for biasing the source electrode at a preset positive potential; and second voltage biasing means, coupled to said gate electrode of said FET, for biasing the gate electrode at a potential lower than the potential of the source electrode during the operation of said FET, wherein said second voltage biasing means comprises: a transistor having an emitter and a collector; a first resistor having one end coupled to a source power terminal and the other end coupled to the emitter of said transistor; and a second resistor having one end coupled to the collector of said transistor and the other end grounded.
Claim 5
Dependent Claim
42 words
The amplifier according to claim 2, wherein said second voltage biasing means further comprises a third resistor having one end coupled to the collector of said transistor and the other end coupled to the gate electrode of said FET via strip lines.
Claim 6
Dependent Claim
15 words
The amplifier according to claim 1, wherein said FET is a high-electron-mobility, gallium-arsenide, field-effect transistor.
Claim 7
Dependent Claim
26 words
The amplifier according to claim 1, wherein said amplifier is a first-stage amplifier provided for use in a low-noise amplifying unit of a global-positioning-system receiving subsystem.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-20 | 2000-02-19 | 2000-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-20 | 2004-02-19 | 2004-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-20 | 2008-02-19 | 2008-08-20 | $7700.00 | Window Closed / Lapsed |