MOS gate driver for ballast circuits

Claim 2

An integrated circuit formed in a silicon substrate for driving first and second MOS gated power devices which are connected in a half bridge circuit which has first and second d-c terminals and a common terminal at the node between said first and second MOS gated power devices; said integrated circuit including timer circuit means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second MOS devices are switched on and off and having an output which is switched in response to a predetermined signal applied to said input control terminal; a high side dead time delay circuit and a low side dead time delay circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means, and said low side driver means coupled to said high side dead time circuit and said low side dead time circuit respectively and having high side and low side output pins respectively which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices.

Claim 3

The integrated circuit of claim 1 wherein said MOS gated power devices are MOS devices which are selected from the group consisting of power MOSFETs, IGBTs and MOS gated thyristors.

Claim 4

The integrated circuit of claim 1 wherein said predetermined time delay is about 1 microsecond.

Claim 5

The circuit of claim 1 which further includes a source of operating voltage V CC coupled to said first and second d-c terminals for providing operating power for each of said circuit means in said integrated circuit; said integrated circuit having a V CC pin extending therefrom for connection to at least one of said first or second d-c terminals.

Claim 6

The circuit of claim 4 which further includes resistor means for coupling said V CC pin to said first d-c terminal.

Claim 7

The integrated circuit of claim 4 wherein said predetermined time delay is about 1 microsecond.

Claim 8

The integrated circuit of claim 5 wherein said predetermined time delay is about 1 microsecond.

Claim 9

The device of claim 4 which further includes undervoltage trip circuit means coupled to and monitoring the voltage at said V CC pin and having an output coupled to said latch circuit means and to said high side and low side dead time circuits for disabling said latch circuit means and delay circuits when the voltage at said V CC pin falls below a given value.

Claim 10

The integrated circuit of claim 8 wherein said predetermined time delay is about 1 microsecond.

Claim 11

The circuit of claim 9 which further includes a source of operating voltage V CC coupled to said first and second d-c terminals for providing operating power for each of said circuit means in said integrated circuit, said integrated circuit having a V CC pin extending therefrom for connection to at least one of said first or second d-c terminals.

Claim 12

The circuit of claim 7 which further includes resistor means for coupling said V CC pin to said first d-c terminal.

Claim 13

The circuit of claim 8 which further includes resistor means for coupling said V CC pin to said positive terminal.

Claim 14

The device of claim 1 wherein said timer circuit has a second input control terminal R T for controlling the frequency at which said MOS gated devices are turned on and off; said terminals C T and R T being connected to an external timing capacitor of value C T and timing resistor of value R T respectively for setting the oscillation frequency f o of said timing circuit to be: ##EQU6##

Claim 15

The integrated circuit of claim 13 wherein said predetermined time delay is about 1 microsecond.

Claim 16

The circuit of claim 13 which further includes a source of operating voltage V CC coupled to said first and second d-c terminals for providing operating power for each of said circuit means in said integrated circuit; said integrated circuit having a V CC pin extending therefrom for connection to at least one of said first or second d-c terminals.

Claim 17

The circuit of claim 13 which further includes resistor means for coupling said V CC pin to said first d-c terminal.

Claim 18

The device of claim 13 which further includes undervoltage trip circuit means coupled to and monitoring the voltage of said V CC pin and having an output coupled to said latch circuit means and to said high side and low side dead time circuits for disabling said latch circuit means and delay circuits when the voltage at said V CC pin falls below a given value.

Claim 19

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said discrete devices; said gate drive circuit having a terminal V CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V CC to one of said pair of terminals.

Claim 20

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said discrete devices; said gate drive circuit having a terminal V CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V CC to one of said pair of terminals.

Claim 21

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices, said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said power switching devices; said gate drive circuit having an oscillation timer circuit having first and second input pins R T and C T respectively, and a discrete resistor and a discrete capacitor connected to pins R T and C T respectively to set said given frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit.

Claim 22

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices, said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said power switching devices; said gate drive circuit having an oscillation timer circuit having first and second input pins R T and C T respectively, and a discrete resistor and a discrete capacitor connected to pins R T and C T respectively to set said given frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit.

Claim 23

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said power switching devices; said gate drive circuit having a terminal V CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V CC to one of said pair of terminals; said gate drive circuit having an oscillation timer circuit having first and second input pins R T and C T respectively, and a discrete resistor and a discrete capacitor connected to pins R T and C T respectively to set said given frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit.

Claim 24

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said power switching devices; said gate drive circuit having a terminal V CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V CC to one of said pair of terminals; said gate drive circuit having an oscillation timer circuit having first and second input pins R T and C T respectively, and a discrete resistor and a discrete capacitor connected to pins R T and C T respectively to set said given frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit.

Claim 25

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a monolithic gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said discrete devices; said gate drive circuit having a terminal V CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V CC to one of said pair of terminals; said integrated circuit including timer means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second power switching devices are switched on and off and having an output which is switched in response to a predetermined signal affixed to said input control terminal; a high side dead time delay circuit and a low side dead time circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit and said low side dead time circuit means respectively and having high side and low side output pins respectively which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices.

Claim 26

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a monolithic gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said discrete devices; said gate drive circuit having a terminal V CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V CC to one of said pair of terminals; said integrated circuit including timer means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second power switching devices are switched on and off and having an output which is switched in response to a predetermined signal affixed to said input control terminal; a high side dead time delay circuit and a low side dead time circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit and said low side dead time circuit means respectively and having high side and low side output pins respectively which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices.

Claim 27

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said MOS power switching devices; said gate drive circuit having an oscillation timer circuit having first and second input pins R T and C T , respectively, and a discrete resistor and a discrete capacitor connected to pins R T and C T , respectively, to set said frequency of oscillation at a given frequency and at the frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit; said integrated circuit including timer means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second discrete devices are switched on and off and having an output which is switched in response to a predetermined signal affixed to said input control terminal; a high side dead time delay circuit and a low side dead time circuit each coupled to said RS latch circuit for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit means and said low side dead time circuit means respectively and having high side and low side output pins respectively which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminals C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices.

Claim 28

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H O and L O coupled to the respective gates of said MOS power switching devices; said gate drive circuit having an oscillation timer circuit having first and second input pins R T and C T , respectively, and a discrete resistor and a discrete capacitor connected to pins R T and C T , respectively, to set said frequency of oscillation at a given frequency and at the frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit; said integrated circuit including timer means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second discrete devices are switched on and off and having an output which is switched in response to a predetermined signal affixed to said input control terminal; a high side dead time delay circuit and a low side dead time circuit each coupled to said RS latch circuit for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit means and said low side dead time circuit means respectively and having high side and low side output pins respectively which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminals C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices.