US5545590A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Conductive rie-resistant collars for studs beneath rie-defined wires
Assignee: International Business Machines Corp
•
Filing: 1994-08-29
•
Granted: 1996-08-13
•
Expires: 2014-08-29
Abstract
Abstract An improved method of forming interlayer interconnections employs the same material (or materials that are etched similarly) for both the stud and the upper interconnect in which the stud is surrounded by a collar of conductive material that is also resistant to the etching process used to define the upper wire interconnect.
Inventors
- 👤 Thomas J. Licata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:44
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
144 words
A method of forming an interconnection member in an integrated circuit containing at least one lower conductive member covered by a first interlayer dielectric having a dielectric top surface, comprising the steps of: forming an aperture having aperture sidewalls in said first interlayer dielectric; forming an interlayer aperture collar of Cu on said aperture sidewalls, said interlayer collar having a collar thickness greater than or equal to a nominal wire stud misalignment, being substantially constant vertically through said aperture, having a conductivity greater than about 75 μΩ-cm and having etch resistance to an upper etching process; forming a first layer of an upper conductive material on said dielectric top surface and extending in said aperture in contact with said interlayer collar; and patterning said upper conductive material with said upper etching process, whereby exposed portions of said interlayer collar resist etching during said patterning.
Claim 2
Independent Claim
144 words
A method of forming an interconnection member in an integrated circuit containing at least one lower conductive member covered by a first interlayer dielectric having a dielectric top surface, comprising the steps of: forming an aperture having aperture sidewalls in said first interlayer dielectric; forming an interlayer aperture collar of Cu on said aperture sidewalls, said interlayer collar having a collar thickness greater than or equal to a nominal wire stud misalignment, being substantially constant vertically through said aperture, having a conductivity greater than about 75 μΩ-cm and having etch resistance to an upper etching process; forming a first layer of an upper conductive material on said dielectric top surface and extending in said aperture in contact with said interlayer collar; and patterning said upper conductive material with said upper etching process, whereby exposed portions of said interlayer collar resist etching during said patterning.
Claim 3
Dependent Claim
78 words
A method according to claim 1, in which said first layer of an upper conductive material formed on said dielectric top surface and extending in said aperture in contact with said interlayer collar is a stud material and said layer of stud material is planarized coplanar with said dielectric top surface, after which a second layer of upper conductive material is formed on said dielectric top surface and in contact with said stud material and said interlayer collar.
Claim 4
Dependent Claim
21 words
A method according to claim 2, in which said stud material and said second upper conductive material are the same material.
Claim 5
Dependent Claim
20 words
A method according to claim 2, in which said stud material and said second upper conductive material are different materials.
Claim 6
Independent Claim
146 words
A method of forming an interconnection member in an integrated circuit containing at least one lower conductive member covered by a first interlayer dielectric having a dielectric top surface, comprising the steps of: forming an aperture having aperture sidewalls in said first interlayer dielectric; forming an interlayer aperture collar of Al 2 Cu on said aperture sidewalls, said interlayer collar having a collar thickness greater than or equal to a nominal wire stud misalignment, being substantially constant vertically through said aperture, having a conductivity greater than about 75 μΩ-cm and having etch resistance to an upper etching process; forming a first layer of an upper conductive material on said dielectric top surface and extending in said aperture in contact with said interlayer collar; and patterning said upper conductive material with said upper etching process, whereby exposed portions of said interlayer collar resist etching during said patterning.
Claim 7
Independent Claim
146 words
A method of forming an interconnection member in an integrated circuit containing at least one lower conductive member covered by a first interlayer dielectric having a dielectric top surface, comprising the steps of: forming an aperture having aperture sidewalls in said first interlayer dielectric; forming an interlayer aperture collar of Al 2 Cu on said aperture sidewalls, said interlayer collar having a collar thickness greater than or equal to a nominal wire stud misalignment, being substantially constant vertically through said aperture, having a conductivity greater than about 75 μΩ-cm and having etch resistance to an upper etching process; forming a first layer of an upper conductive material on said dielectric top surface and extending in said aperture in contact with said interlayer collar; and patterning said upper conductive material with said upper etching process, whereby exposed portions of said interlayer collar resist etching during said patterning.
Claim 8
Dependent Claim
78 words
A method according to claim 5, in which said first layer of an upper conductive material formed on said dielectric top surface and extending in said aperture in contact with said interlayer collar is a stud material and said layer of stud material is planarized coplanar with said dielectric top surface, after which a second layer of upper conductive material is formed on said dielectric top surface and in contact with said stud material and said interlayer collar.
Claim 9
Dependent Claim
20 words
A method according to claim 6, in which said collar of Al 2 Cu is deposited in a single step.
Claim 10
Dependent Claim
53 words
A method according to claim 6, in which said collar of Al 2 Cu is formed by the steps of depositing a first layer of one of Al and Cu, depositing a second layer of the other of Al and Cu, and reacting said first and second layers to form Al 2 Cu.
References Cited (Backward Citations)
US4589196A
Cited
US4666737A
Cited
US5270254A
Cited
JPH05166750A
Cited
JPH0621218A
Cited
US5356833A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-13 | 2000-02-12 | 2000-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-13 | 2004-02-12 | 2004-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-13 | 2008-02-12 | 2008-08-13 | $7700.00 | Window Closed / Lapsed |