US5545576A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a thin film transistor panel
Assignee: Samsung Display Co Ltd
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Filing: 1995-04-21
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Granted: 1996-08-13
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Expires: 2015-04-21
Abstract
Abstract A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.
Inventors
- 👤 Hiroshi Matsumoto
- 👤 Haruo Wakai
- 👤 Hiroyasu Joubettou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:20
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0231; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/6737; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6757; H10D86/40; H10D86/60; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; Y; Y10; Y10S; Y10S148/00; Y10S148/102
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
145 words
A method for manufacturing a thin film transistor panel comprising: a first step of forming a gate electrode and a gate line on a transparent insulating substrate; a second step of successively forming a gate insulating film, a semiconductor thin film and an insulating film on the gate electrode, the gate line and the transparent insulating substrate; a third step of patterning the insulating film into a shape which is self-aligned with the gate electrode and the gate line by means of exposure through the transparent substrate; a fourth step of forming, on the insulating film, a mask having a length which extends across the gate electrode at right angles; a fifth step of etching at least the insulating film and the semiconductor thin film using the mask; and a sixth step of removing the mask, thereby forming a source electrode and a drain electrode.
Claim 2
Independent Claim
145 words
A method for manufacturing a thin film transistor panel comprising: a first step of forming a gate electrode and a gate line on a transparent insulating substrate; a second step of successively forming a gate insulating film, a semiconductor thin film and an insulating film on the gate electrode, the gate line and the transparent insulating substrate; a third step of patterning the insulating film into a shape which is self-aligned with the gate electrode and the gate line by means of exposure through the transparent substrate; a fourth step of forming, on the insulating film, a mask having a length which extends across the gate electrode at right angles; a fifth step of etching at least the insulating film and the semiconductor thin film using the mask; and a sixth step of removing the mask, thereby forming a source electrode and a drain electrode.
Claim 3
Dependent Claim
45 words
The method according to claim 1, wherein the fourth step includes a step of forming a metal conductive film, which can form a silicide, on the insulating film and the semiconductor thin film, and a step of forming the mask on the metal conductive film.
Claim 4
Dependent Claim
31 words
The method according to claim 2, wherein the fourth step includes a step of forming a metal silicide on a surface of the semiconductor thin film from the metal conductive film.
Claim 5
Dependent Claim
30 words
The method according to claim 1, wherein the third step includes a step of diffusing an ion impurity into the semiconductor thin film using the insulating film as a mask.
References Cited (Backward Citations)
WO1987004565A1
Cited
US4790630A
Cited
US4990460A
Cited
US5270229A
Cited
JPH0360042A
Cited
JPH0488641A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-13 | 2000-02-12 | 2000-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-13 | 2004-02-12 | 2004-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-13 | 2008-02-12 | 2008-08-13 | $7700.00 | Window Closed / Lapsed |