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US5541799A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reducing the natural current limit in a power MOS device by reducing the gate-source voltage
Assignee: Texas Instruments Inc
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Filing: 1994-06-24
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Granted: 1996-07-30
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Expires: 2014-06-24
Abstract
Abstract In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I D so that MOS device 110 is not damaged by the short circuit condition.
Inventors
- 👤 Thomas A. Schmidt
- 👤 Ross E. Teggatz
- 👤 Joseph A. Devore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:31
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/082; H03K17/0822
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
107 words
A method of protecting a power MOS device of an integrated circuit from an excessive drain current, the device having a source, a gate with a gate-source voltage thereon, and a drain connected to an output terminal of the integrated circuit; the method comprising: sensing the drain current in the power MOS device, and, in response to excessive drain current, reducing the gate-source voltage by coupling between the gate and the source a facility that reduces the gate-source voltage to a predetermined substantially constant value that is sufficiently low to sufficiently increase the resistance of the device to a value whereat the drain current is not excessive.
Claim 2
Independent Claim
107 words
A method of protecting a power MOS device of an integrated circuit from an excessive drain current, the device having a source, a gate with a gate-source voltage thereon, and a drain connected to an output terminal of the integrated circuit; the method comprising: sensing the drain current in the power MOS device, and, in response to excessive drain current, reducing the gate-source voltage by coupling between the gate and the source a facility that reduces the gate-source voltage to a predetermined substantially constant value that is sufficiently low to sufficiently increase the resistance of the device to a value whereat the drain current is not excessive.
Claim 3
Dependent Claim
35 words
The method of claim 1 of protecting a power MOS device of an integrated circuit from an excessive drain current, wherein the step of sensing drain current further comprises: detecting a predetermined trigger current value.
Claim 4
Dependent Claim
56 words
The method of claim 1 of protecting a power MOS device of an integrated circuit from an excessive drain current, further comprising: sensing the drain current in the power MOS device, and, in response to the removal of excessive drain current; restoring the gate-source voltage to a value that existed before sensing the excessive drain current.
Claim 5
Dependent Claim
54 words
The method of claim 2 of protecting a power MOS device of an integrated circuit from an excessive drain current, wherein the step of reducing the gate-source voltage further comprises: reducing the gate-source voltage to a predetermined substantially constant value so that a resulting limited drain current is less than the trigger current value.
Claim 6
Dependent Claim
64 words
The method of claim 2 of protecting a power MOS device of an integrated circuit from an excessive drain current, wherein the step of detecting the trigger current further comprises: forming a sense voltage which is proportional to the drain current; comparing the sense voltage to a predetermined reference voltage; and detecting the trigger current value when the sense voltage exceeds the reference voltage.
Claim 7
Dependent Claim
130 words
The method of claim 2 of protecting a power MOS device of an integrated circuit from an excessive drain current, wherein the step of detecting the trigger current further comprises: forming a sense voltage which is proportional to the drain current; generating a predetermined reference trigger current that is a known ratio of the trigger current; creating a reference voltage which is proportional to the reference trigger current by conducting the reference trigger current through a transistor which is similar to the power MOS device so that a variation in an operating parameter of the power MOS device is compensated for by a similar variation in the transistor; and comparing the sense voltage to the reference voltage; and detecting the trigger current when the sense voltage exceeds the reference voltage.
Claim 8
Dependent Claim
89 words
The method of claim 1 of protecting a power MOS device of an integrated circuit from an excessive drain current, wherein the step of reducing the gate-source voltage further comprises: connecting an impedance device in series with an input terminal and the gate of the power MOS device; and coupling a device having an approximately fixed voltage drop across the gate and source of the power MOS device so that a portion of the gate-source voltage in excess of the fixed voltage drop is dropped across the impedance device.
Claim 9
Dependent Claim
92 words
The method of claim 1 of protecting a power MOS device of an integrated circuit from an excessive drain current, wherein the step of reducing the gate-source voltage further comprises: connecting a first impedance device in series with an input terminal and the gate of the power MOS device; and coupling a second impedance device across the gate and source of the power MOS device to form an impedance divider network having an approximately fixed impedance ratio so that a portion of the gate-source voltage is dissipated across the first impedance device.
Claim 10
Dependent Claim
148 words
The method of claim 1 of protecting a power MOS device of an integrated circuit from an excessive drain current, wherein the step of reducing the gate-source voltage further comprises: connecting an impedance device in series with an input terminal and the gate of the power MOS device; generating a reference limited current that is a known ratio of the limited drain current; generating a limited gate-source voltage that is proportional to the reference limited current by conducting the reference limited current through a transistor similar to the power MOS device so that a variation in an operating parameter of the power MOS device is compensated for by a similar variation in the transistor; and coupling the limited gate-source voltage across the gate and source of the power MOS device and dissipating a portion of the gate-source voltage that exceeds the limited drive voltage across the impedance device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-30 | 2000-01-29 | 2000-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-30 | 2004-01-29 | 2004-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-30 | 2008-01-29 | 2008-07-30 | $7700.00 | Window Closed / Lapsed |