Signal processing circuit including a variable gain input stage

Claim 2

Processing circuit (2, 120) for producing a variable output signal in response to a variable quantity picked up or received as input, said processing circuit being associated with a stage or having an input sensor (4, 100) furnishing a signal with a variable amplification/attenuation factor and said processing circuit further exhibiting response characteristics which depend in particular from a state variable of at least one circuit element of said processing circuit, characterized in that it includes means (FIG. 5, FIG. 6) for suppressing transients normally produced by modification of said amplification/attenuation factor, said means for suppressing transients functioning by modifying the value of said state variable of said circuit element in direct proportion to said modification of the amplification/attenuation factor.

Claim 3

Processing circuit according to claim 1, characterized in that said circuit is a filter.

Claim 4

Processing circuit according to claim 1, characterized in that said circuit is a sigma-delta band pass modulator.

Claim 5

Processing circuit according to claim 1, characterized in that said means for suppressing transients comprise a switched capacitor circuit element controlled by a sequencer.

Claim 6

Processing circuit according to claim 1, characterized in that said means for suppressing transients comprise a multiplier provided for multiplying a current by the intensity of a signal corresponding to the factor by which the gain of said input stage is modified.

Claim 7

Processing circuit according to claim 1, characterized in that the means for suppressing transients (FIG. 3) are provided to modify the values of the state variables in predetermined relationships.

Claim 8

Processing circuit according to claim 1, characterized in that the means for suppressing transients (FIG. 4) are provided to change the state variables by an arbitrary factor.

Claim 9

Processing circuit for an analog signal provided to produce a variable output signal in response to a variable input signal, including an input stage with variable gain amplification/attenuation, the response characteristics of said circuit depending from a state variable of at least one circuit element of said processing circuit among others, characterized in that in includes means for suppressing transients normally produced by a modification of the gain of said input stage, said means for suppression of the transients functioning by modifying the value of said state variable of said circuit element as a direct proportion of said modification of the gain.

Claim 10

Processing circuit for an analog signal provided to produce a variable output signal in response to a variable input signal, including an input stage with variable gain amplification/attenuation, the response characteristics of said circuit depending from a state variable of at least one circuit element of said processing circuit among others, characterized in that in includes means for suppressing transients normally produced by a modification of the gain of said input stage, said means for suppression of the transients functioning by modifying the value of said state variable of said circuit element as a direct proportion of said modification of the gain.

Claim 11

Processing circuit according to claim 1, characterized in that it is a sigma-delta converter for converting a variable input signal into said variable output signal, comprising signal combining means (221) for adding or subtracting said output signal from said input signal so as to produce a combined signal, integrating means (222) for integrating said combined signal so as to produce an integrated signal, said integrating means having error storage means (238) for storing a quantity representative of the temporal value of said combined signal, comparator means (223) for comparing said integrated signal to one or more pre-defined levels so as to produce said output signal, feedback means (224) for supplying a feedback signal representative of said output signal to said combining means, range setting means (226) for altering said amplification/attenuation factor between a first value and at least a second value, means (27) to amplify said output signal by the inverse of said amplification/attenuation factor, and noise compensation means (28) for multiplying said stored quantity by the ratio of said second value to said first value when said amplification/attenuation factor is changed from said first value to said second value.

Claim 12

Processing circuit according to claim 9, characterized in that said integrating means (222) comprises an amplifier (237) having an inverting input, a non-inverting input and an output, and said error storage means (238) comprises a storage capacitance connected between said inverting input and said amplifier output, said storage capacitance (238) storing a charge proportional to said temporal value of said difference signal.

Claim 13

Processing circuit according to claim 10, characterized in that said noise compensation means (228) comprises means for multiplying the value of said storage capacitance, and thus said quantity of stored charge, by said ratio.

Claim 14

Processing circuit according to claim 10, characterized in that said noise compensation means (228) comprises at least one additional capacitance (245) connectable either in series with said storage capacitance (238), or in parallel with said storage capacitance (238).

Claim 15

Processing circuit according to claim 12, characterized in that said storage capacitance (238) and said additional capacitance (245) have the same value.

Claim 16

Processing circuit according to any one of the claim 9, characterized in that said input signal comprises an analog voltage, said input signal amplifying means (225) comprising an input capacitance (229,230,231,232), connected to said integrating means (222), for converting said analog voltage into a charge representative of said amplified input signal, said range setting means (226) comprising means (233,234,235,236) to alter the value of said input capacitance.

Claim 17

Processing circuit according to claim 14, characterized in that said input signal amplifying means (225) comprises a plurality of capacitive elements (229,230,231,232), said range setting means (226) comprising switching means (229,230,231,232) for connecting one or more of said capacitive elements in parallel.

Claim 18

Processing circuit according to claim 15, characterized in that said capacitive elements (29,30,31,32) have the same value.

Claim 19

Processing circuit according to claim 9, characterized in that said input signal comprises a measurable capacitance connectable to said integrating means (222), said input signal amplifying means comprising an preselected input voltage applied across said measurable capacitance for converting said measurable capacitance into a charge representative thereof, said range setting means (226) comprising means to alter the value of said input voltage.

Claim 20

Processing circuit according to claim 9, characterized in that said input signal comprises an analog current supplied to said integrating means (222), said input signal amplifying means (225) comprising amplifier means to amplify said analog current, said range setting means (226) comprising means to alter the amplification of said amplifier means.

Claim 21

Processing circuit according to claim 9, characterized in that said input signal is variable digital quantity, said integrating means (281) comprising a digital accumulator (284) for storing a digital value of n bits representative of said temporal value of said combined signal, said digital accumulator (284) having an input and an output, and means (285) for adding the digital value from said accumulator (284) output to said combined signal.

Claim 22

Processing circuit according to claim 19, characterized in that said noise compensation means comprises means (292) for altering said digital value stored in said accumulator.

Claim 23

Processing circuit according to claim 20, characterized in that said comparator means comprises a truncator (282) for separating said digital value into its m most-significant-bits (Y msb ) and its (n-m) least-significant-bits (Y 1sb ), said output signal (Y out ) comprising said m most significant bits.

Claim 24

Processing circuit according to claim 21, characterized in that said (n-m) least-significant-bits are added to said combined signal so as to provide said accumulator input signal, said accumulator output being supplied directly to said truncator, said noise compensating means multiplying said (n-m) least-significant-bits by said ratio.

Claim 25

Processing circuit according to claim 22, characterized in that said ratio equals a power of 2, said noise compensating means comprising means for shifting said (n-m) least-significant-bits to more significant positions in said digital value.

Claim 26

Processing circuit according to claim 1, characterized in that it is a sigma-delta converter for converting a variable input signal into a variable output signal, comprising signal combining means (301) for adding or subtracting a feedback signal representative of said output signal from said input signal so as to produce a combined signal, integrating means (222) for integrating said combined signal so as to produce an integrated signal, said integrating means having error storage means (238) for storing a quantity representative of the temporal value of said combined signal, comparator means (222) for comparing said integrated signal to one or more pre-defined levels so as to produce said output signal, means (302) to amplify said output signal by said amplification/attenuation factor so as to provide said feedback signal, and range setting means (303) for altering said amplification/attenuation factor between a first value and at least a second value.

Claim 27

Processing circuit according to claim 24, characterized in that said output signal amplifying means (302) comprises a feedback capacitance (305,306,307,308), connected to said integrating means, for converting said output signal into a charge representative thereof, said range setting means comprising means (309,310,311, 312) to alter the value of said feedback capacitance.

Claim 28

Processing circuit according to claim 25, characterized in that said output signal amplifying means (302) comprises a plurality of capacitive elements (305,306,307,308), said range setting means (303) comprises switching means (309,310,311,312) for connecting one or more of said capacitive elements in parallel.

Claim 29

Processing circuit according to claim 26, characterized in that said capacitive elements (305,306,307,308) have the same value.

Claim 30

Processing circuit according to claim 24, characterized in that said input signal is variable digital quantity, said integrating means (281) comprises a digital accumulator (284) for storing a digital value of n bits representative of said temporal value of said combined signal, said digital accumulator (284) having an input and an output, said comparator means comprising a truncator (321) for separating said digital value into its m most-significant-bits and its (n-m) least-significant-bits.

Claim 31

Processing circuit according to claim 28, characterized in that a number of said (n-m) least-significant-bits are added to said difference signal so as to provide said accumulator input signal, said accumulator output being supplied directly to said truncator (321), wherein said range selection means alters the number of said bits added to said difference signal.

Claim 32

Processing circuit according to claim 9, characterized in that it further comprises first gain control means (340) for measuring said input signal and producing a gain signal (G) representative of said amplification/attenuation factor for use by said range setting means (226).

Claim 33

Processing circuit according to claims 9, characterized in that it further comprises second gain control means (350) for measuring said output signal and producing a gain signal (G) representative of said amplification/attenuation factor for use by said range setting means (226).

Claim 34

Oversampled digital/analog converter (270) including a processing circuit according to claim 9, characterized in that it further comprises an interpolating filter (272) for sampling a digital input signal so as to supply a sampled signal of n bits, an elementary digital/analog converter (273) for supplying an analog signal representative of said digital input signal, said sigma-delta converter (271) receiving said n bits of sampled signal and supplying a noise-shaped signal of m bits representative of said sampled signal to said elementary digital/analog converter (273).

Claim 35

Oversampled digital/analog converter (330) including a processing circuit according to claims 9, characterized in that it further comprises an input branch having a digital/analog converter (331) for converting a digital difference signal into an analog difference signal, and an integrator (332) for integrating said analog difference signal so as to produce an analog output signal, a feedback branch having an sigma-delta analog/digital converter (333) for converting said analog output signal into a digital feedback signal, and signal combining means for combining an analog input signal with said feedback signal so as to produce said combined signal.