← Back to Patent Explorer
US5541129A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making non-volatile memory device

Assignee: Toshiba Corp
•
Filing: 1994-08-15
•
Granted: 1996-07-30
•
Expires: 2014-08-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor memory device such as an EEPROM having an insulation layer with a dielectric constant greater than that of SiO 2 formed beneath a floating gate on or below a tunnel oxide layer where the passage of electrons is enabled by means of tunnel effect in order to increase the dielectric breakdown voltage of the tunnel oxide layer. The semiconductor memory device is made by a method in which, for example, a thin Si 3 N 4 layer is formed on a thin SiO 2 tunnel oxide layer or a substrate, and the layered structure is patterned to leave only a tunnel part. Then a SiO 2 gate insulation layer is formed over the substrate and the tunnel part, followed by formation of a floating gate on the SiO 2 gate insulation layer and diffusion of impurities into the floating gate. The Si 3 N 4 portion of the tunnel part prevents diffused impurities from reaching the SiO 2 tunnel oxide of the tunnel part or the substrate. Further, patterning of the tunnel part before formation of the SiO 2 gate insulation layer avoids contamination of the SiO 2 gate insulation layer. Thus, the dielectric breakdown voltage of the SiO 2 tunnel oxide of the tunnel part and the SiO 2 gate insulation layer is increased.

Inventors

  • 👤 Hiroaki Tsunoda

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/00; H10D64/01; H10D64/031; H10D64/035

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 92 words
A method of manufacturing a semiconductor memory device, comprising the steps of: forming a first insulation layer on a semiconductor substrate; forming a second insulation layer on the first insulation layer; removing the second insulation layer except for a tunnel insulation part where electrons formed in the substrate are enabled to pass through, without removing the first insulation layer in order to form an exposed first insulation layer; forming a third insulation layer by oxidizing the exposed first insulation layer; and forming a polysilicon layer on the third and second insulation layers.
Claim 2
Independent Claim 92 words
A method of manufacturing a semiconductor memory device, comprising the steps of: forming a first insulation layer on a semiconductor substrate; forming a second insulation layer on the first insulation layer; removing the second insulation layer except for a tunnel insulation part where electrons formed in the substrate are enabled to pass through, without removing the first insulation layer in order to form an exposed first insulation layer; forming a third insulation layer by oxidizing the exposed first insulation layer; and forming a polysilicon layer on the third and second insulation layers.
Claim 3
Dependent Claim 17 words
The method of claim 1, further comprising the step of: diffusing an impurity into the polysilicon layer.

References Cited (Backward Citations)

US4115914A Cited
US4385308A Cited
US4630086A Cited
JPS5966171A Cited
US5008721A Cited
US5017979A Cited
US5063423A Cited
US5138410A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-07-30 2000-01-29 2000-07-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-07-30 2004-01-29 2004-07-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-07-30 2008-01-29 2008-07-30 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag