Vector data processing apparatus wherein a time slot for access to a bank of vector registors is assigned based on memory access time information

Claim 1

A vector data processing apparatus for receiving and executing vector instructions, including vector load instructions which instruct an operation including access to a main storage, said vector data processing apparatus comprising: said main storage unit for storing data; a set of vector registers, each vector register arranged in a plurality of banks, each bank being simultaneously and independently accessible; at least one memory access pipeline for transferring the data between said main storage and said set of vector registers as specified by vector load instructions, selected data being transferred as specified by a respective vector load instruction when the respective vector load instruction is received by the vector data processing apparatus; and vector unit control means for controlling cyclical accessing to the plurality of banks of said vector registers, by the at least one memory access pipeline, said vector unit control means further comprising: vector load instruction detecting means for detecting reception of a vector load instruction by one of the at least one vector load pipeline, and for outputting a memory access detection signal in response to the detection of said vector load instruction, time slot timing generating means for generating a time slot timing signal, indicative of timings of cyclical time slots through which said cyclical accessing to the plurality of banks of said vector register is allowed, and outputting said time slot timing signal, model information storing means for storing model information obtained in advance of operation of said vector processing apparatus, said model information being data specific to said vector data processing apparatus, being indicative of a minimum time required to fetch said data from said main storage unit for writing said transferred data in one of said plurality of banks of said vector registers, said model information for determining an optimum time slot among time slots other than those used for other pipelines for each possible time at which said vector load detection signal can be received, and instruction time slot assigning means for receiving said vector load detection signal, said model information, and said time slot timing signal, and for assigning, at a time of memory access, said optimum time slot to said vector load instruction which is detected by the vector load instruction detecting means, based on a time at which said vector load detection signal is received by said instruction time slot assigning means with respect to the timings indicated by said time slot timing signal, and referring to said model information.