Method to ensure data integrity in a telecommunications network

Claim 1

A method for generating and checking a Frame Check Sequence (FCS) for a message formed as a sequence of n-bit data bytes and inserting said FCS at the end of said message, comprising performing a computation operation on said sequence of data bytes in order to generate said FCS by processing each of said n-bit data bytes,in successive cycles, characterized in that said computation operation comprises the following steps: a. sequentially receiving said sequence of n-bit data bytes of said message; b. pushing each data byte of said sequence of n-bit data bytes into a shift register, until said shift register is full; c. multiplying the contents of said shift register at each cycle by a vector belonging to the Galois Field that matches the number of bits of said n-bit data byte processed at each cycle; d. updating the contents of said shift register by loading the result of said multiplying step into said shift register; e. pushing a new byte of data from said sequence of n-bit data bytes into said shift register; f. repeating steps c, d, e until all the n-bit data bytes from said sequence of n-bit data bytes have been pushed into said shift register.

Claim 2

A method for generating and checking a Frame Check Sequence (FCS) for a message formed as a sequence of n-bit data bytes and inserting said FCS at the end of said message, comprising performing a computation operation on said sequence of data bytes in order to generate said FCS by processing each of said n-bit data bytes,in successive cycles, characterized in that said computation operation comprises the following steps: a. sequentially receiving said sequence of n-bit data bytes of said message; b. pushing each data byte of said sequence of n-bit data bytes into a shift register, until said shift register is full; c. multiplying the contents of said shift register at each cycle by a vector belonging to the Galois Field that matches the number of bits of said n-bit data byte processed at each cycle; d. updating the contents of said shift register by loading the result of said multiplying step into said shift register; e. pushing a new byte of data from said sequence of n-bit data bytes into said shift register; f. repeating steps c, d, e until all the n-bit data bytes from said sequence of n-bit data bytes have been pushed into said shift register.

Claim 6

The method according to any one of claims 1-4 wherein, at initialization the content of said shift register is preset to all ones.

Claim 8

An apparatus for generating and checking a Frame Check Sequence (FCS) for a message formed as a sequence of n-bit data bytes and inserting said FCS at the end of said message wherein the n-bit data bytes of said message are sequentially received and a computation operation on said sequence of n-bit data bytes is performed in successive cycles in order to generate said FCS, said apparatus comprising: a shift register having a number of positions equal to the number of bits in said FCS and into which each n-bit data byte of said sequence of n-bit data bytes is pushed until said shift register is full; a Galois Field multiplier activated at each cycle to multiply the contents of said shift register by a vector of the Galois Field; gating circuitry to load said shift register with the result of said Galois Field multiplication; and means for pushing a new n-bit data byte of said sequence of n-bit data bytes into said shift register with said shift register containing a current FCS at each cycle.

Claim 9

An apparatus for generating and checking a Frame Check Sequence (FCS) for a message formed as a sequence of n-bit data bytes and inserting said FCS at the end of said message wherein the n-bit data bytes of said message are sequentially received and a computation operation on said sequence of n-bit data bytes is performed in successive cycles in order to generate said FCS, said apparatus comprising: a shift register having a number of positions equal to the number of bits in said FCS and into which each n-bit data byte of said sequence of n-bit data bytes is pushed until said shift register is full; a Galois Field multiplier activated at each cycle to multiply the contents of said shift register by a vector of the Galois Field; gating circuitry to load said shift register with the result of said Galois Field multiplication; and means for pushing a new n-bit data byte of said sequence of n-bit data bytes into said shift register with said shift register containing a current FCS at each cycle.