Multiple bank column redundancy intialization controller for cache RAM

Claim 2

A circuit for initializing a set of memory banks during a reset state, each memory bank having a set of N primary columns configured adjacent and parallel to each other and adjacent to M redundant columns configured adjacent and parallel to each other where "N" and "M" are predetermined whole numbers, comprising: a storage circuit including a plurality of storage devices corresponding to each of said set of memory banks, wherein a first plurality of said plurality of storage devices stores detective column indicators representing a location of at least one defective column within a first memory bank of said set of memory banks and a second plurality of said plurality of storage devices stores detective column indicators representing a location of at least one defective column within a second memory bank of said set of memory banks; a master control circuit, coupled to said storage circuit, configured to generate a maximum clock cycle value, a plurality of clock signals and a signal indicating completion of the reset state; a counter circuit, coupled to said master control circuit, configured to generate a series of binary signals based on said maximum clock cycle value, said binary signals collectively representing a count value; and a set of bank controllers, corresponding to each of said set of memory banks, wherein a first bank controller of said set of bank controllers, coupled to said first plurality of storage devices and said master control circuit, is configured to (i) generate a first set of shift signals based on said plurality of clock signals, said series of binary signals, and said defective column indicators associated with the first plurality of storage devices and (ii) transmit said first set of shift signals into said first memory bank, and a second bank controller of said set of bank controllers, coupled to said second plurality of storage devices and said master control circuit, is configured to (i) generate a second set of shift signals based on said plurality of clock signals, said series of binary signals, and said defective column indicators associated with the second plurality of storage devices and (ii) transmit said second set of shift signals into said second memory bank.

Claim 3

The circuit of claim 1, wherein said counter circuit generates said series of binary signals to be used to calculate both said first and second set of shift signals.

Claim 4

The circuit of claim 1, wherein each of said plurality of storage devices provides storage for at least log 2 (N+M) bits, log 2 ((N+M)/M) bits for indicating a group of M columns adjacent to a first group of M columns contains said at least one defective column, and log 2 (M) bits for indicating a first defective column within said first group of M columns contains said at least one defective column; said maximum clock cycle value is equal to (N+M)/M; and each of said plurality of clock signals including M overlapping series of non-overlapping clock cycles, each of said M overlapping series having at least (N+M)/M clock cycles.

Claim 5

The circuit of claim 3, wherein M equals 2; each of said plurality of storage devices provides storage for at least log 2 (N+2) bits, log 2 ((N+2)/2) bits for indicating a group of two columns adjacent to a first group of two columns contains at least one defective column, a first bit for indicating a first defective column within said first group of two columns; said maximum clock cycle value stored in said first circuit is equal to (N+2)/2; and said plurality of clock signals includes a first and a second overlapping series of non-overlapping clock cycles, said first series having (N+2)/2 clock cycles, said second series having (N+2)/2 clock cycles if said first bit has a logic value of "0" to indicate that a first defective column is within said first group of two columns and ((N+2)/2)+1) clock cycles if said first bit has a logic value of "1" to indicate that a first defective column within said first group of two columns.

Claim 6

The circuit as set forth in claim 3, wherein each of said plurality of shift signals includes a first series and a second series of signals; and said first series being generated before one of said series of binary signals produces said count value equal to log 2 ((N+M)/M), and said second series being generated thereafter, said first and second series of signals being "shift" and "not shift" signals respectively, if said counter circuit is decrementing said count value and alternatively "not shift" and "shift" signals respectively, if said counter circuit is incrementing said count value.

Claim 7

The circuit as set forth in claim 1, said storage circuit includes a master "no-defect" indicator, coupled to said master control circuit, to indicate that none of said N primary columns are defective, wherein said master control circuit generates each of said plurality of clock signals based on (i) said maximum clock cycle value if said master "no-defect" indicator is not set, and alternatively (ii) said master "no-defect" indicator if said master "no-defect" indicator is set, and said set of bank controllers generates each of said series of shift signals based on (i) said stored maximum clock cycle value if said master "no-defect" indicator is not set, and alternatively said master "no-defect" indicator if said "no-defect" indicator is set.

Claim 8

The circuit as set forth in claim 6, wherein said master "no-defect" indicator is a master fuse.

Claim 9

The circuit as set forth in claim 6, wherein said maximum clock cycle value stored in said master control circuit is equal to (N+M)/M and said plurality of clock signals generated by said master control circuit includes M overlapping series of non-overlapping clock cycles, each of said M series of clock cycles having (N+M)/M clock cycles.

Claim 10

The circuit of claim 6, wherein each of said plurality of storage devices is a fuse.

Claim 11

A computer system comprising: a bus for transmitting data; a display, coupled to said bus, for displaying said data; a input device, coupled to said bus, for receiving said data; a memory circuit, coupled to said bus, for storing said data; a microprocessor, coupled to said bus, for processing said data; and an integrated circuit, coupled to said bus, providing a set of shift signals for initializing a set of memory banks during a reset state, each memory bank having a set of N primary columns configured adjacent and parallel to each other and adjacent to M redundant columns configured adjacent and parallel to each other where "N" and "M" are predetermined whole numbers, said integrated circuit including a storage circuit including a plurality of storage devices corresponding to each of said set of memory banks, wherein a first plurality of said plurality of storage devices stores defective column indicators representing a location of at least one defective column within a first memory bank of said set of memory banks and a second plurality of said plurality of storage devices stores detective column indicators representing a location of at least one defective column within a second memory bank of said set of memory banks, a master control circuit, coupled to said storage circuit, configured to generate a maximum clock cycle value, a plurality of clock signals and a signal indicating completion of the reset state, a counter circuit, coupled to said master control circuit, configured to generate a series of binary signals using said maximum clock cycle value, said binary signals collectively representing a count value, and a set of bank controllers, corresponding to each of said set of memory banks, wherein a first bank controller of said set of bank controllers, coupled to said first plurality of storage devices and said master control circuit, is configured to (i) generate a first set of shift signals based on said plurality of clock signals, said series of binary signals, and said defective column indicators associated with the first plurality of storage devices and (ii) transmit said first set of shift signals into said first memory bank and a second bank controller of said set of bank controllers, coupled to said second plurality of storage devices and said master control circuit, is configured to (i) generate a second set of shift signals based on said plurality of clock signals, said series of binary signals, and said defective column indicators associated with the second plurality of storage devices and (ii) transmit said second set of shift signals into said second memory bank.

Claim 12

A computer system comprising: a bus for transmitting data; a display, coupled to said bus, for displaying said data; a input device, coupled to said bus, for receiving said data; a memory circuit, coupled to said bus, for storing said data; a microprocessor, coupled to said bus, for processing said data; and an integrated circuit, coupled to said bus, providing a set of shift signals for initializing a set of memory banks during a reset state, each memory bank having a set of N primary columns configured adjacent and parallel to each other and adjacent to M redundant columns configured adjacent and parallel to each other where "N" and "M" are predetermined whole numbers, said integrated circuit including a storage circuit including a plurality of storage devices corresponding to each of said set of memory banks, wherein a first plurality of said plurality of storage devices stores defective column indicators representing a location of at least one defective column within a first memory bank of said set of memory banks and a second plurality of said plurality of storage devices stores detective column indicators representing a location of at least one defective column within a second memory bank of said set of memory banks, a master control circuit, coupled to said storage circuit, configured to generate a maximum clock cycle value, a plurality of clock signals and a signal indicating completion of the reset state, a counter circuit, coupled to said master control circuit, configured to generate a series of binary signals using said maximum clock cycle value, said binary signals collectively representing a count value, and a set of bank controllers, corresponding to each of said set of memory banks, wherein a first bank controller of said set of bank controllers, coupled to said first plurality of storage devices and said master control circuit, is configured to (i) generate a first set of shift signals based on said plurality of clock signals, said series of binary signals, and said defective column indicators associated with the first plurality of storage devices and (ii) transmit said first set of shift signals into said first memory bank and a second bank controller of said set of bank controllers, coupled to said second plurality of storage devices and said master control circuit, is configured to (i) generate a second set of shift signals based on said plurality of clock signals, said series of binary signals, and said defective column indicators associated with the second plurality of storage devices and (ii) transmit said second set of shift signals into said second memory bank.

Claim 13

The computer system of claim 10, wherein said counter circuit generates said series of binary signals to be used to calculate both said first and second set of shift signals.

Claim 14

The computer system of claim 10, wherein each of said plurality of storage devices provides storage for at least log 2 (N+M) bits, log 2 ((N+M)/M) bits used to indicate a group of M columns adjacent to a first group of M columns contains said at least one defective column, and log 2 (M) bits used to indicate a first defective column within said first group of M columns contains said at least one defective column; said maximum clock cycle value is equal to (N+M)/M; and each of said plurality of clock signals include M overlapping series of non-overlapping clock cycles, each of said M overlapping series having at least (N+M)/M clock cycles.

Claim 15

The computer system of claim 12, wherein: M equals 2; each of said plurality of storage devices comprises at least log 2 (N+2) bits, log 2 ((N+2)/2) bits being used to indicate a group of two columns adjacent to a first group of two columns contains at least one defective column, a first bit being used to indicate a first defective column within said first group of two columns contains at least one defective column; said maximum clock cycle value stored in said first circuit is equal to (N+2)/2; and said plurality of clock signals includes a first and a second overlapping series of non-overlapping clock cycles, said first series having (N+2)/2 clock cycles, said second series having (N+2)/2 clock cycles if said first bit has a logic value of "0" to indicate that a first defective column is within said first group of two columns and ((N+2)/2)+1) clock cycles if said first bit has a logic value of "1" for indicating a first defective column within said first group of two columns.

Claim 16

The computer system of claim 12, wherein each of said plurality of shift signals includes a first series and a second series of signals; and said first series being generated before one of said series of binary signals produces said count value equal to said log 2 ((N+M)/M), and said second series being generated afterwards, said first and second series of signals being "shift" and "not shift" signals respectively if said counter circuit is decrementing said count value, and alternatively "not shift" and "shift" signals respectively if said counter circuit is incrementing its count value.

Claim 17

The computer system of claim 10, further comprising: a master "no-defect" indicator, coupled to said master control circuit, to indicate that none of said N primary columns are defective, wherein said master control circuit generates each of said plurality of clock signals based on said maximum clock cycle value if said master "no-defect" indicator is not set, and alternatively said master "no-defect" indicator if said master "no-defect" indicator is set, and said set of bank controllers generates each of said series of shift signals based on said maximum clock cycle value if said master "no-defect" indicator is not set, and alternatively, said master "no-defect" indicator if said master "no-defect" indicator is set.

Claim 18

The circuit of claim 15, wherein said master "no-defect" indicator is a master fuse.

Claim 19

The computer system as set forth in claim 15, wherein said maximum clock cycle value stored in said master control circuit is equal to (N+M)/M and said plurality of clock signals generated by said master control circuit includes M overlapping series of non-overlapping clock cycles, each of said M series of clock cycles having (N+M)/M clock cycles.

Claim 20

The computer system of claim 17, wherein M equals 2; said maximum clock cycle value stored in said master control circuit is equal to (N+2)/2; and said plurality of clock signals generated by said master control circuit includes a first and a second overlapping series of non-overlapping clock cycles, each series having (N+2)/2 clock cycles.

Claim 21

The computer system 10 of claim 10, wherein each of said plurality of storage devices is a fuse.