Patent US5537538A successfully refreshed from Google Patents.
US5537538A
Expired / Lapsed
US
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Debug mode for a superscalar RISC processor
Assignee: ARM Finance Overseas Ltd
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Filing: 1993-12-15
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Granted: 1996-07-16
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Expires: 2013-12-15
Abstract
Abstract A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.
Inventors
- 👤 Joseph P. Bratt
- 👤 John Brennan
- 👤 Peter Y. Hsu
- 👤 Chandra S. Joshi
- 👤 William A. Huffman
- 👤 Monica R. Nofal
- 👤 Paul Rodman
- 👤 Joseph T. Scanlon
- 👤 Man K. Tang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:21
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/3698; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/3854; G06F9/3858; G06F9/3861; G06F9/3867; G06F9/3885
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
151 words
A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation, the processor system comprising: means for dispatching integer and floating point instructions; an integer unit, coupled to said means for dispatching, having a multi-stage integer pipeline for executing said integer instructions; a floating point unit, coupled to said means for dispatching and said integer unit, having a multi-stage floating point pipeline for executing said floating point instructions; and means, coupled to said means for dispatching, for switching the system between the normal mode of operating and the debug mode of operation thereby preventing instructions from being committed after a floating point instruction is dispatched when the system is in the debug mode until the system determines whether said floating point instruction generates an exception, thus permitting the system to signal precise exceptions when not in the normal mode.
Claim 2
Dependent Claim
151 words
A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation, the processor system comprising: means for dispatching integer and floating point instructions; an integer unit, coupled to said means for dispatching, having a multi-stage integer pipeline for executing said integer instructions; a floating point unit, coupled to said means for dispatching and said integer unit, having a multi-stage floating point pipeline for executing said floating point instructions; and means, coupled to said means for dispatching, for switching the system between the normal mode of operating and the debug mode of operation thereby preventing instructions from being committed after a floating point instruction is dispatched when the system is in the debug mode until the system determines whether said floating point instruction generates an exception, thus permitting the system to signal precise exceptions when not in the normal mode.
Claim 3
Dependent Claim
35 words
The system according to claim 1, wherein said means for dispatching starts to dispatch further instructions one or more floating point pipeline stages before the system determines whether said floating point instruction generates an exception.
Claim 4
Independent Claim
116 words
A method for operating a processor system in a debug mode, wherein the system is switchable between a normal mode of operation without precise floating point exceptions and the debug mode, the method comprising the step of: determining whether the system has been switched to the debug mode; dispatching a floating point instruction; and switching the system between the normal mode of operating and the debug mode of operation thereby preventing instructions from being committed after a floating point instruction is dispatched when the system is in the debug mode until the system determines whether said floating point instruction generates an exception, thus permitting the system to signal precise exceptions when not in the normal mode.
Claim 5
Independent Claim
116 words
A method for operating a processor system in a debug mode, wherein the system is switchable between a normal mode of operation without precise floating point exceptions and the debug mode, the method comprising the step of: determining whether the system has been switched to the debug mode; dispatching a floating point instruction; and switching the system between the normal mode of operating and the debug mode of operation thereby preventing instructions from being committed after a floating point instruction is dispatched when the system is in the debug mode until the system determines whether said floating point instruction generates an exception, thus permitting the system to signal precise exceptions when not in the normal mode.
Claim 6
Dependent Claim
30 words
The method according to claim 3, further comprising the step of dispatching further instructions one or more cycles before the system determines whether said floating point instruction generated an exception.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |