Frame buffer address generator for the mulitple format display of multiple format source video

Claim 1

A video imaging system comprising: an image memory for storing a plurality of images, wherein each of said images has a plurality of pixels; a video display having a matrix of pixels; a programmable address generator for producing a user defined sequence of display frames, each of which includes an ordered set of pixels from said image memory, and which is characterized by an ordered set of addresses, one for each display pixel, and an ordered set of pixel group identifiers, one for each display pixel; wherein said address generator includes a) a programmable mapping memory for storing a pixel descriptor of each display pixel of a display frame, said pixel descriptor including a pixel group identification field, which identifies a group of pixels of said video display, and an address field which includes address information of said image memory of pixels to be displayed; and b) an address manager, which is linked to said mapping memory and said video display, and which has a set of registers and logic circuitry corresponding to each of said pixel groups of said mapping memory and said display, wherein each said set of registers includes a sum register, a delta register, and a mask register, the collective function of each said sets of registers and corresponding logic circuitry being to modify the address field of a pixel descriptor from said mapping memory to retrieve an image pixel stored in said image memory for display on said video display; and a control for controlling said video imaging system to sequentially read out said pixel descriptors from said mapping memory, and to process said address field of each read out pixel descriptor, by the pixel group set of registers and logic circuitry of said address manager, which corresponds to the pixel group identifier of said processed pixel descriptor, a) in a display mode, in which the mask register specifies bits of the address field, which may or may not be contiguous, to be modified, by adding the masked bits of the address field of the pixel descriptor to the respective bits of the sum register, by which process a modified address field is generated, whose unmasked bits are composed of the original and respective bits of the address field, and whose masked bits are generated as a result of the latter process; and b) in a frame advance mode in which the mask register specifies bits of the sum register, which are contiguous or not, to be modified, wherein the masked bits of the sum register are added to the respective bits of the delta register, to generate a modified value, whose unmasked bits are composed of the original address field bits and respective bits of the sum register, and whose masked bits are generated by the latter process.