Semiconductor device having thin film transistor with diffusion preventing layer

Claim 2

A thin film transistor, comprising: source/drain regions formed in a thin semiconductor layer which is formed on a semiconductor substrate with an insulating film therebetween, said source/drain regions containing impurity of a first conductivity type and defining a channel region sandwiched between said source region and said drain region, said channel region having ends overlapping a portion of said source/drain regions; and a gate electrode formed at a position opposed to said channel region with a gate insulating film therebetween, wherein a diffusion preventing layer for preventing diffusion of impurity is formed on at least one of interfaces between said channel region and said source/drain regions, wherein said diffusion preventing layer extends from a region between said gate electrode and said channel region to a position above said source/drain regions.

Claim 3

The thin film transistor according to claim 1, wherein said diffusion preventing layer is formed at the interface between said drain region and said channel region.

Claim 4

The thin film transistor according to claim 1, wherein said diffusion preventing layers are formed at the interface between said drain region and said channel region and at the interface between said source region and said channel region.

Claim 5

The thin film transistor according to claim 1, wherein said diffusion preventing layer is a dielectric film.

Claim 6

The thin film transistor according to claim 1, wherein the thickness of said diffusion preventing layer is 30 Å, or less.

Claim 7

The thin film transistor according to claim 2, wherein said diffusion preventing layer formed at the interface between said drain region and said channel region is located at a position spaced by a predetermined distance from said gate electrode in a channel length direction of said thin film transistor.

Claim 8

The thin film transistor according to claim 1, wherein said channel region is formed of a first semiconductor layer, and said source/drain regions are formed of a pair of second semiconductor layers.

Claim 9

The thin film transistor according to claim 7, wherein said diffusion preventing layer extends between said first semiconductor layer and said gate electrode and over surfaces of said pair of second semiconductor layers.

Claim 10

The thin film transistor according to claim 7, wherein a width of said first semiconductor layer in the channel width direction of said thin film transistor is at least a width of said second semiconductor layer in the channel width direction.

Claim 11

The thin film transistor according to claim 1, wherein said diffusion preventing layer is selected from the group consisting of a titanium nitride film and a silicon nitride film.

Claim 12

A semiconductor device having a thin film transistor, comprising: a first conductive layer formed in a thin semiconductor layer which is formed on a semiconductor substrate with an insulating film therebetween, said first conductive layer containing impurity of a first conductivity type and forming source/drain regions of a thin film transistor; a second conductive layer formed on said semiconductor substrate, said second conductive layer being electrically connected to said first conductive layer and containing impurity of a second conductivity type; and a connection conductive layer formed between said first and second conductive layers and containing impurity of the first conductivity type, wherein concentration of said impurity of the first conductivity type contained in said connection conductive layer is lower than that of said impurity of the first conductivity type contained in said first conductive layer.

Claim 13

A semiconductor device having a thin film transistor, comprising: a first conductive layer formed in a thin semiconductor layer which is formed on a semiconductor substrate with an insulating film therebetween, said first conductive layer containing impurity of a first conductivity type and forming source/drain regions of a thin film transistor; a second conductive layer formed on said semiconductor substrate, said second conductive layer being electrically connected to said first conductive layer and containing impurity of a second conductivity type; and a connection conductive layer formed between said first and second conductive layers and containing impurity of the first conductivity type, wherein concentration of said impurity of the first conductivity type contained in said connection conductive layer is lower than that of said impurity of the first conductivity type contained in said first conductive layer.

Claim 14

The semiconductor device having a thin film transistor according to claim 11, wherein a diffusion preventing layer is formed at the interface between said connection conductive layer and said second conductive layer.

Claim 15

A semiconductor device having a thin film transistor, comprising: a pair of first impurity regions of a first conductivity type formed in a thin semiconductor layer formed on a main surface of a semiconductor substrate of a first conductivity type with an insulating film posed therebetween, to define a first channel region; a first gate electrode formed at a position opposite to said first channel region with a gate insulating film posed therebetween; a conductive layer of a second conductivity type formed on the main surface of said semiconductor substrate and connected to one of said first impurity regions; a connection conductive layer formed between one of said first impurity regions and said conductive layer and including an impurity of the first conductivity type; a pair of second impurity regions of the second conductivity type formed on the main surface of said semiconductor substrate to define a second channel region, one of which is connected to said conductive layer; and a second gate electrode formed on said second channel region with a gate insulating film posed therebetween; wherein impurity concentration of the first conductivity type included in said connection conductive layer is lower than impurity concentration of the first conductivity type included in said first impurity regions.

Claim 16

A semiconductor device having a thin film transistor, comprising: a pair of first impurity regions of a first conductivity type formed in a thin semiconductor layer formed on a main surface of a semiconductor substrate of a first conductivity type with an insulating film posed therebetween, to define a first channel region; a first gate electrode formed at a position opposite to said first channel region with a gate insulating film posed therebetween; a conductive layer of a second conductivity type formed on the main surface of said semiconductor substrate and connected to one of said first impurity regions; a connection conductive layer formed between one of said first impurity regions and said conductive layer and including an impurity of the first conductivity type; a pair of second impurity regions of the second conductivity type formed on the main surface of said semiconductor substrate to define a second channel region, one of which is connected to said conductive layer; and a second gate electrode formed on said second channel region with a gate insulating film posed therebetween; wherein impurity concentration of the first conductivity type included in said connection conductive layer is lower than impurity concentration of the first conductivity type included in said first impurity regions.

Claim 17

The semiconductor device having a thin film transistor according to claim 13, wherein an impurity diffusion preventing layer is formed between said connection conductive layer and said conductive layer.

Claim 18

The semiconductor device having a thin film transistor according to claim 14, wherein said impurity diffusion preventing layer is selected from the group consisting of a titanium nitride layer and a silicon nitride layer.

Claim 19

The semiconductor device having a thin film transistor according to claim 13, wherein an impurity diffusion preventing layer is formed between said first impurity regions and said first channel region.