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US5536685A Expired / Lapsed US ⏱️ 0.0 years remaining

Low heat loss and secure chip carrier for cryogenic cooling

Assignee: Sun Microsystems Inc
•
Filing: 1995-06-06
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Granted: 1996-07-16
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Expires: 2015-06-06
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Abstract

Abstract An integrated circuit package is disclosed. The integrated circuit package includes a substrate having a cavity formed therein for enclosing an integrated circuit. The integrated circuit package also includes a carrier for holding the integrated circuit. The carrier is positioned within the cavity of the substrate. A thermally reactive connector is coupled to the carrier. The thermally reactive connector is for selectively coupling the carrier to the substrate when a temperature of the thermally reactive connector is above a first temperature such that the carrier is held in position within the opening. The thermally reactive connector is also for decoupling the carrier from the substrate when the carrier temperature is at the first temperature. In this manner, the number of thermal paths between the integrated circuit and the substrate of the integrated circuit is reduced.

Inventors

  • 👤 Trevor Burward-Hoy

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 17:54
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/30; H10W40/305; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49169; Y10T29/49171; Y10T29/49172

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 138 words
A process for manufacturing a cryogenic cooling system for an integrated chip, the process comprising the steps of: attaching the integrated circuit to a carrier having a thermally reactive connector attached thereto; positioning the carrier within a bottom opening of a substrate of a semiconductor package, the semiconductor package having a cavity defined by a side wall, the bottom opening, and a top opening, the carrier being positioned such that the integrated circuit extends into the cavity; coupling the carrier to the substrate via the thermally reactive connector when a carrier temperature of the carrier is at an ambient temperature such that the thermally reactive connector holds the carrier in place within the opening of the substrate; attaching at least one bond wire between the integrated circuit and the carrier; and covering the top opening with a lid.
Claim 2
Dependent Claim 138 words
A process for manufacturing a cryogenic cooling system for an integrated chip, the process comprising the steps of: attaching the integrated circuit to a carrier having a thermally reactive connector attached thereto; positioning the carrier within a bottom opening of a substrate of a semiconductor package, the semiconductor package having a cavity defined by a side wall, the bottom opening, and a top opening, the carrier being positioned such that the integrated circuit extends into the cavity; coupling the carrier to the substrate via the thermally reactive connector when a carrier temperature of the carrier is at an ambient temperature such that the thermally reactive connector holds the carrier in place within the opening of the substrate; attaching at least one bond wire between the integrated circuit and the carrier; and covering the top opening with a lid.
Claim 3
Dependent Claim 107 words
The process of claim 1, wherein the process comprises the further steps of: coupling the carrier to a cooling apparatus, the cooling apparatus having an outer wall for enclosing the bottom opening and a cold probe for cooling the carrier, the cold probe being enclosed within the outer wall such that a chamber is formed between the outer wall and the cold probe, the chamber being in atmospheric communication with the cavity via the bottom opening; evacuating the chamber and the cavity; and cooling the carrier such that the thermally reactive connector automatically decouples the carrier from the substrate when the carrier temperature reaches a first temperature.

References Cited (Backward Citations)

US4716124A Cited
US5219795A Cited
US5142443A Cited
US5346859A Cited
US5387554A Cited
US5280409A Cited
US5257162A Cited
US5461258A Cited
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US5381041A Cited
US5476818A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-07-16 2000-01-15 2000-07-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-07-16 2004-01-15 2004-07-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-07-16 2008-01-15 2008-07-16 $7700.00 Window Closed / Lapsed

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