Abstract There is disclosed a method for the fabrication of semiconductor device. A problem of short circuit that a metal wiring comes into contact with an area of a silicon substrate which area, when a contact hole is formed, is exposed due to misalignment of the metal wiring mask can be prevented by formation of an oxide layer in a lower area of the contact hole. The method comprises the steps of: forming a field oxide layer on a predetermined area of a silicon substrate; forming a conductive layer pattern in such a way that it overlaps with the filed oxide layer, the conductive layer pattern insulated from the silicon substrate; forming a blanket interlayer insulation film over the resulting structure; etching a contact region of the interlayer insulation film, to form a contact hole which exposes an area of the conductive layer pattern, an area of the field oxide layer being etched owing to misalignment of the contact mask and an area of the silicon substrate being exposed through the contact hole; selectively depositing an epitaxial single crystal silicon on the exposed area of the silicon substrate; oxidizing the epitaxial single crystal silicon at a predetermined thickness, to form an oxide layer; and forming a metal wiring which is electrically connected with the conductive layer pattern and electrically insulated from the silicon substrate.
A method for the fabrication of semiconductor device, comprising the steps of: forming a field oxide layer on an area of a silicon substrate; forming a conductive layer pattern in such a way that it overlaps with the field oxide layer, said conductive layer pattern being insulated from the silicon substrate; forming a blanket interlayer insulation film over the resulting structure; etching a contact region of the interlayer insulation film using a contact mask, to form a contact hole which exposes an area of the conductive layer pattern, an area of the field oxide layer being etched owing to misalignment of the contact mask, an area of said silicon substrate being exposed through said contact hole; selectively depositing an epitaxial single crystal silicon on the exposed area of the silicon substrate; oxidizing at least a portion of the epitaxial single crystal silicon to form an oxide layer; and forming a metal wiring which is electrically connected with the exposed area of the conductive layer pattern and electrically insulated from the silicon substrate.
Claim 2
Independent Claim
172 words
A method for the fabrication of semiconductor device, comprising the steps of: forming a field oxide layer on an area of a silicon substrate; forming a conductive layer pattern in such a way that it overlaps with the field oxide layer, said conductive layer pattern being insulated from the silicon substrate; forming a blanket interlayer insulation film over the resulting structure; etching a contact region of the interlayer insulation film using a contact mask, to form a contact hole which exposes an area of the conductive layer pattern, an area of the field oxide layer being etched owing to misalignment of the contact mask, an area of said silicon substrate being exposed through said contact hole; selectively depositing an epitaxial single crystal silicon on the exposed area of the silicon substrate; oxidizing at least a portion of the epitaxial single crystal silicon to form an oxide layer; and forming a metal wiring which is electrically connected with the exposed area of the conductive layer pattern and electrically insulated from the silicon substrate.
Claim 3
Dependent Claim
16 words
A method in accordance with claim 1, wherein said conductive layer pattern is a gate electrode.
Claim 4
Dependent Claim
29 words
A method in accordance with claim 1, wherein said contact hole is formed after a film which is different in etch selectivity from the interlayer insulation film is deposited.
Claim 5
Dependent Claim
20 words
A method in accordance with claim 1, wherein said epitaxial single crystal silicon is oxidized by ion-implantation of oxygen atoms.
Claim 6
Dependent Claim
18 words
A method in accordance with claim 1, wherein said conductive layer pattern is capped with a silicide layer.