US5536676A
Expired / Lapsed
US
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Low temperature formation of silicided shallow junctions by ion implantation into thin silicon films
Assignee: National Science and Technology Council
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Filing: 1995-04-03
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Granted: 1996-07-16
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Expires: 2015-04-03
Abstract
Abstract A method for forming silicided shallow junctions, wherein impurities are implanted into a silicon layer formed over a silicon substrate. A metal layer selected from one of platinum (Pt), palladium (Pd), nickel (Ni) and cobalt (Co) is deposited over the silicon layer. At least one low temperature annealing process is carried out to form a silicide layer as well as the shallow junctions. Pre-anneal of the silicon layer and post-anneal of the silicide between 450 DEG and 600 DEG C. are also employed.
Inventors
- 👤 Huang-Chung Cheng
- 👤 Cheng-Tung Lin
- 👤 Chi-Hung Chao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:25
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10P32/14; H10P32/1408; H10P32/1414
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
116 words
A method for forming shallow junctions on a silicon substrate of a first conductivity type comprising the steps of: forming a silicon layer over said silicon substrate; implanting impurities of a second conductivity type into said silicon layer; pre-annealing said silicon layer at a temperature in a range between about 450° and 600° C.; forming a metal layer over said silicon layer; annealing said silicon layer and said metal layer to form a metal silicide layer, thus driving said impurities into said silicon substrate and forming shallow junctions therein; removing unreacted metal; and post-annealing said metal silicide layer at a temperature in a range between about 450° and 600° C. for forming a stable silicide layer.
Claim 2
Independent Claim
116 words
A method for forming shallow junctions on a silicon substrate of a first conductivity type comprising the steps of: forming a silicon layer over said silicon substrate; implanting impurities of a second conductivity type into said silicon layer; pre-annealing said silicon layer at a temperature in a range between about 450° and 600° C.; forming a metal layer over said silicon layer; annealing said silicon layer and said metal layer to form a metal silicide layer, thus driving said impurities into said silicon substrate and forming shallow junctions therein; removing unreacted metal; and post-annealing said metal silicide layer at a temperature in a range between about 450° and 600° C. for forming a stable silicide layer.
Claim 3
Dependent Claim
28 words
The method of claim 1 further comprising a predip step prior to the formation of said silicon layer for removing a native oxide layer over said silicon substrate.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein said silicon substrate of first conductivity type is an N-type silicon substrate, and said impurities of second conductivity type are P-type impurities.
Claim 5
Dependent Claim
19 words
The method of claim 3, wherein said silicon layer is a polysilicon layer having a thickness of about 1500Å.
Claim 6
Dependent Claim
14 words
The method of claim 3, wherein said silicon layer is an amorphous silicon layer.
Claim 7
Dependent Claim
36 words
The method of claim 3, wherein said implanting step is carried out by implanting BF 2 + ions at an implanting energy between 75 and 125 KeV and a dose between 1E15 and 1E16/cm 2 .
Claim 8
Dependent Claim
20 words
The method of claim 6, wherein said metal layer is a platinum (Pt) layer having a thickness of about 1000Å.
Claim 9
Dependent Claim
16 words
The method of claim 7, wherein said metal silicide layer is a platinum silicide (PtSi) layer.
Claim 10
Dependent Claim
20 words
The method of claim 6, wherein said metal layer is a palladium (Pd) layer having a thickness of about 2000Å.
Claim 11
Dependent Claim
18 words
The method of claim 9, wherein said metal silicide layer is a palladium silicide (Pd 2 Si) layer.
Claim 12
Dependent Claim
19 words
The method of claim 10 wherein said annealing step is carried out at a temperature of about 300° C.
Claim 13
Dependent Claim
20 words
The method of claim 6, wherein said metal layer is a nickel (Ni) layer having a thickness of about 700Å.
Claim 14
Dependent Claim
16 words
The method of claim 12, wherein said metal silicide layer is a nickel silicide (NiSi) layer.
Claim 15
Dependent Claim
20 words
The method of claim 6, wherein said metal layer is a cobalt (Co) layer having a thickness of about 300Å.
Claim 16
Dependent Claim
18 words
The method of claim 14, wherein said metal silicide layer is a cobalt silicide (CoSi 2 ) layer.
Claim 17
Dependent Claim
26 words
The method of claim 8, 13 or 15 wherein said annealing step is carried out at a temperature of about 400° C. for about 60 minutes.
Claim 18
Dependent Claim
16 words
The method of claim 1, wherein said pre-annealing step is carried out for about 60 minutes.
Claim 19
Dependent Claim
16 words
The method of claim 1, wherein said post-annealing step is carried out for about 60 minutes.
Claim 20
Dependent Claim
28 words
The method of claim 1, wherein said silicon substrate of first conductivity type is a P-type silicon substrate, and said impurities of second conductivity type are N-type impurities.
References Cited (Backward Citations)
US4764480A
Cited
US5302539A
Cited
US4966868A
Cited
US5302552A
Cited
US5403772A
Cited
US5254495A
Cited
US5409853A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |