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Patent US5535237A successfully refreshed from Google Patents.
US5535237A
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Method and system for a multi channel and search global position system signal processor
Assignee: Texas Instruments Inc
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Filing: 1994-02-04
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Granted: 1996-07-09
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Expires: 2014-02-04
Abstract
Abstract There is disclosed a multi channel GPS digital signal processor on a single IC. Each channel contains circuitry to process L1 or L2 P(Y) and C/A-code signals. In addition a search processor is included to achieve fast signal acquisition. Low power adder/accumulators have been designed to provide for a high precision digital oscillator whose output is synchronous to a high speed clock. The IC contains a full low power null detector and eight correlators to aid in signal acquisition.
Inventors
- 👤 Leonard J. LaPadula, III
- 👤 George W. Pawlowski
- 👤 David W. Rekieta
- 👤 Hugh L. Scott
- 👤 Chyi H. Lu
- 👤 John P. Volpi
- 👤 Mitchel B. Stiles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:07
CPC Classifications
G; G01; G01S; G01S19/00; G01S19/01; G01S19/13; G01S19/24; G01S19/21; G01S19/32; G01S19/35; G01S19/37; H; H04; H04B; H04B2201/00; H04B2201/69; H04B2201/707; H04B2201/70715
Claims Analysis
Total Claims: 78
Claim 1
Independent Claim
61 words
A digital signal processing (DSP) circuit for use in a global positioning system (GPS) receiver, said DSP circuit comprising, on a single integrated circuit (IC): Y-code generator circuitry; and at least one signal processing channel, said channel including circuitry means for processing at least one of a valid P-code signal and Y-code signal from at least one satellite of said GPS.
Claim 2
Dependent Claim
61 words
A digital signal processing (DSP) circuit for use in a global positioning system (GPS) receiver, said DSP circuit comprising, on a single integrated circuit (IC): Y-code generator circuitry; and at least one signal processing channel, said channel including circuitry means for processing at least one of a valid P-code signal and Y-code signal from at least one satellite of said GPS.
Claim 3
Dependent Claim
16 words
The circuit set forth in claim 1 wherein said DSP includes circuitry for processing C/A code.
Claim 4
Dependent Claim
18 words
The circuit set forth in claim 2 wherein said DSP includes: circuitry for tracking C/A and P-code simultaneously.
Claim 5
Dependent Claim
18 words
The circuit set forth in claim 1 wherein said DSP includes circuitry for processing P-code or Y-code selectively.
Claim 6
Dependent Claim
16 words
The circuit set forth in claim 4 wherein said DSP includes circuitry for processing multiple channels.
Claim 7
Dependent Claim
27 words
The circuitry set forth in claim 5 wherein said Y-code on any said channel is generated by a single Y-code generator common to all said multiple channels.
Claim 8
Dependent Claim
16 words
The circuitry set forth in claim 1 wherein said DSP includes circuitry for processing multiple channels.
Claim 9
Dependent Claim
25 words
The circuitry set forth in claim 7 wherein said DSP includes: a noise meter per channel for aiding in said acquiring or tracking of signal.
Claim 10
Dependent Claim
26 words
The circuitry set forth in claim 7 wherein said DSP includes circuitry for allowing one channel to generate a test signal for use by other channels.
Claim 11
Dependent Claim
17 words
The circuitry set forth in claim 1 further comprising: circuitry for selectively processing L1 or L2 signals.
Claim 12
Dependent Claim
20 words
The circuitry set forth in claim 1 wherein said DSP includes: circuitry for establishing programmable integration periods for signal correlation.
Claim 13
Dependent Claim
23 words
The circuitry set forth in claim 1 wherein said DSP includes a noise meter for aiding in said acquiring or tracking of signal.
Claim 14
Dependent Claim
19 words
The circuitry set forth in claim 1 wherein said DSP includes circuitry for supporting full null zone signal inputs.
Claim 15
Dependent Claim
18 words
The circuitry set forth in claim 1 wherein said DSP includes a search processor for fast signal acquisition.
Claim 16
Dependent Claim
16 words
The circuitry set forth in claim 14 wherein said search processor includes a fourier transform function.
Claim 17
Dependent Claim
28 words
The circuitry set forth in claim 15 wherein said search processor further includes circuitry to interpolate new frequency bins between the frequency bins of said fourier transform function.
Claim 18
Dependent Claim
16 words
The circuitry set forth in claim 14 wherein said search processor includes a Tong detection algorithm.
Claim 19
Dependent Claim
34 words
The circuitry set forth in claim 17 wherein said search processor further includes frequency bin mask bits which exclude certain frequency bins of said fourier transform from being considered in said Tong detection algorithm.
Claim 20
Dependent Claim
29 words
The circuitry set forth in claim 17 wherein said search processor further includes correlator mask bits which exclude certain code states from being considered in said Tong detection algorithm.
Claim 21
Dependent Claim
31 words
The circuitry set forth in claim 14 wherein said search processor includes: a mush counter for controlling the time that said digital signal processing circuitry attempts to acquire any particular signal.
Claim 22
Dependent Claim
29 words
The circuitry set forth in claim 14 wherein said search processor includes: a mush counter for providing an indication of either a bad signal or a bad search threshold.
Claim 23
Dependent Claim
28 words
The circuitry set forth in claim 14 wherein said search processor further includes a hit counter for aiding in the determination of the adequacy of a search threshold.
Claim 24
Dependent Claim
22 words
The circuitry set forth in claim 14 wherein said search processor further includes a threshold calculator which autonomously adjusts for noise level.
Claim 25
Dependent Claim
36 words
The circuitry set forth in claim 23 wherein said threshold calculator further includes the calculation of a second threshold for the interpolated frequency bins which is the square root of 2 greater than the regular threshold.
Claim 26
Dependent Claim
19 words
The circuitry set forth in claim 14 wherein said search processor utilizes a Robertson approximation to generate correlation envelopes.
Claim 27
Dependent Claim
40 words
The circuitry set forth in claim 1 wherein said DSP further includes a digital oscillator for providing carrier or code clock synchronous to a high frequency reference clock which mostly runs at a significantly lower frequency for reduced power dissipation.
Claim 28
Dependent Claim
24 words
The circuitry set forth in claim 26 wherein said digital oscillator for carrier generation includes circuitry for selective one or two bit carrier generation.
Claim 29
Dependent Claim
39 words
The circuitry set forth in claim 1 wherein said DSP further includes: an adder/accumulator primarily for accumulating only binary multiples, said adder/accumulator including: pulse injectors operating in conjunction with a ripple counter for reduced power dissipation and gate count.
Claim 30
Dependent Claim
31 words
The circuitry set forth in claim 1 wherein said DSP further includes: a correlator configuration including ripple counters for predetection integration bias accumulation; and an adder for subtraction of said bias.
Claim 31
Dependent Claim
15 words
The circuitry set forth in claim 29 wherein said correlator configuration supports adjacent correlator presumming.
Claim 32
Dependent Claim
16 words
The circuitry set forth in claim 29 wherein said correlator configuration supports full null zone operation.
Claim 33
Independent Claim
49 words
A device for use in GPS receivers for processing of multiple digitized satellite signals, said device comprising, on a single application specific integrated circuit (ASIC): Y-code generator circuitry; multiple P(Y) and C/A-code channel means for processing said multiple digitized satellite signals; and a search processor for fast signal acquisition.
Claim 34
Independent Claim
49 words
A device for use in GPS receivers for processing of multiple digitized satellite signals, said device comprising, on a single application specific integrated circuit (ASIC): Y-code generator circuitry; multiple P(Y) and C/A-code channel means for processing said multiple digitized satellite signals; and a search processor for fast signal acquisition.
Claim 35
Dependent Claim
17 words
The device set forth in claim 32 further including: circuitry for tracking said C/A and P(Y)-code simultaneously.
Claim 36
Dependent Claim
16 words
The device set forth in claim 32 further including: circuitry for processing P-code or Y-code selectively.
Claim 37
Dependent Claim
23 words
The device set forth in claim 32 wherein said Y-code is generated by a single Y-code generator common to all said multiple channels.
Claim 38
Dependent Claim
17 words
The device set forth in claim 32 further including: circuitry for selectively processing L1 or L2 signals.
Claim 39
Dependent Claim
18 words
The device set forth in claim 32 further including: circuitry for establishing programmable integration periods for signal correlation.
Claim 40
Dependent Claim
20 words
The device set forth in claim 32 further including: a noise meter for aiding in acquiring or tracking said signals.
Claim 41
Dependent Claim
17 words
The device set forth in claim 32 further including: circuitry for supporting full null zone signal inputs.
Claim 42
Dependent Claim
18 words
The device set forth in claim 32 wherein said search processor includes a fourier transform function implementation circuit.
Claim 43
Dependent Claim
27 words
The device set forth in claim 40 wherein said search processor further includes: circuitry to interpolate new frequency bins between the frequency bins of said fourier transform.
Claim 44
Dependent Claim
18 words
The device set forth in claim 32 wherein said search processor includes a Tong detection algorithm implementation circuit.
Claim 45
Dependent Claim
37 words
The device set forth in claim 42 wherein said search processor further includes: first circuitry means for providing frequency bin mask bits which exclude certain frequency bins from being considered in said Tong detection algorithm implementation circuit.
Claim 46
Dependent Claim
36 words
The device set forth in claim 42 wherein said search processor further includes: second circuitry means for providing correlator mask bits which exclude certain code states from being considered in said Tong detection algorithm implementation circuit.
Claim 47
Dependent Claim
28 words
The device set forth in claim 32 wherein said search processor includes: a mush counter for controlling the time that said processor attempts to acquire any particular signal.
Claim 48
Dependent Claim
29 words
The device set forth in claim 32 wherein said search processor includes: a mush counter for providing an indication of either a bad signal or a bad search threshold.
Claim 49
Dependent Claim
29 words
The device set forth in claim 32 wherein said search processor further includes: a hit counter means for aiding in the determination of the adequacy of a search threshold.
Claim 50
Dependent Claim
22 words
The device set forth in claim 32 wherein said search processor further includes: a threshold calculator which autonomously adjusts for noise level.
Claim 51
Dependent Claim
24 words
The device set forth in claim 48 wherein said threshold calculator further includes: circuitry for calculating a second threshold for the interpolated frequency bins.
Claim 52
Dependent Claim
23 words
The device set forth in claim 32 wherein said search processor further includes: circuitry for utilizing the Robertson approximation to generate correlation envelopes.
Claim 53
Dependent Claim
37 words
The device set forth in claim 32 further including: a digital oscillator for providing carrier or code clock synchronous to a high frequency reference clock which mostly runs at a significantly lower frequency for reduced power dissipation.
Claim 54
Dependent Claim
24 words
The device set forth in claim 51 wherein said digital oscillator for carrier generation includes circuitry for selective one or two bit carrier generation.
Claim 55
Dependent Claim
35 words
The device set forth in claim 32 further including: an adder/accumulator primarily for accumulating only binary multiples, said adder/accumulator including: pulse injectors operating in conjunction with a ripple counter for reducing power and gate count.
Claim 56
Dependent Claim
29 words
The device set forth in claim 32 further including: a correlator configuration using ripple counters for predetection integration and bias accumulation; and an adder for subtraction of said bias.
Claim 57
Dependent Claim
15 words
The device set forth in claim 54 wherein said correlator configuration supports adjacent correlator presumming.
Claim 58
Dependent Claim
16 words
The device set forth in claim 54 wherein said correlator configuration supports full null zone operation.
Claim 59
Dependent Claim
26 words
The device set forth in claim 32 further including: third circuitry means for causing one channel to generate a test signal for use by other channels.
Claim 60
Dependent Claim
19 words
The device set forth in claim 32 further including: circuitry for establishing variable integration periods for signal predetection integration.
Claim 61
Independent Claim
196 words
A device for tracking and acquiring global positioning system (GPS) signals from multiple satellites, said device comprising, on a single integrated circuit: Y-code generator circuitry; two P(Y) and C/A-code channels; a search processor for fast signal acquisition; support circuitry means for processing null zone signals; said channels each comprising: a carrier generator; a code clock generator; a P-code generator; a C/A-code generator; eight predetection integration accumulators; and a noise meter; said search processor comprising: a discrete fourier transform circuit; first circuitry means for performing frequency bin interpolation; second circuitry means for implementing a Robertson approximation for envelope calculation; third circuitry means for implementing a Tong detection algorithm to determine if signal is present; a threshold calculator which uses measurements from said noise meter; fourth circuitry means for calculating a second search threshold for the interpolated frequency bins; fifth circuitry means for advancing or retarding code state as required during search; a mush counter which counts Tong detection iterations for a specific code state and either forces a new code state or stops search; and a hit counter which counts hits associated with a specified number of discrete fourier transform cycles and reports the most current value.
Claim 62
Independent Claim
196 words
A device for tracking and acquiring global positioning system (GPS) signals from multiple satellites, said device comprising, on a single integrated circuit: Y-code generator circuitry; two P(Y) and C/A-code channels; a search processor for fast signal acquisition; support circuitry means for processing null zone signals; said channels each comprising: a carrier generator; a code clock generator; a P-code generator; a C/A-code generator; eight predetection integration accumulators; and a noise meter; said search processor comprising: a discrete fourier transform circuit; first circuitry means for performing frequency bin interpolation; second circuitry means for implementing a Robertson approximation for envelope calculation; third circuitry means for implementing a Tong detection algorithm to determine if signal is present; a threshold calculator which uses measurements from said noise meter; fourth circuitry means for calculating a second search threshold for the interpolated frequency bins; fifth circuitry means for advancing or retarding code state as required during search; a mush counter which counts Tong detection iterations for a specific code state and either forces a new code state or stops search; and a hit counter which counts hits associated with a specified number of discrete fourier transform cycles and reports the most current value.
Claim 63
Dependent Claim
63 words
The device set forth in claim 59 wherein said predetection accumulators include: circuitry for performing adjacent correlator presumming for removal of signal to noise ratio holes between code states; a circuit configuration using ripple counters so as to minimize power consumption and gate count; and a circuit configuration using ripple counters and pulse injectors to minimize power consumption of high frequency sample accumulation.
Claim 64
Dependent Claim
60 words
The device set forth in claim 59 wherein said carrier and code clock generators include: a digital oscillator circuit architecture which generates a carrier or code clock output synchronous to a high frequency clock but mostly runs at a low frequency to minimize power consumption; and a low frequency adder/accumulator using ripple counters and pulse injectors which reduce gate count.
Claim 65
Dependent Claim
21 words
The device set forth in claim 59 further including: a circuit for converting P-code to Y-code which supports both channels simultaneously.
Claim 66
Dependent Claim
16 words
The device set forth in claim 59 further including: circuitry for tracking C/A and P-code simultaneously.
Claim 67
Dependent Claim
18 words
The device set forth in claim 59 further including: circuitry for establishing programmable integration periods for signal correlation.
Claim 68
Dependent Claim
35 words
The device set forth in claim 59 wherein said search processor further includes: sixth circuitry means for providing frequency bin mask bits which exclude certain frequency bins from being considered in said Tong detection algorithm.
Claim 69
Dependent Claim
34 words
The device set forth in claim 59 wherein said search processor further includes: seventh circuitry means for providing correlator mask bits which exclude certain code states from being considered in said Tong detection algorithm.
Claim 70
Dependent Claim
29 words
The device set forth in claim 59 further including: correlator configuration circuitry using ripple counters for predetection integration and bias accumulation; and an adder for subtraction of said bias.
Claim 71
Dependent Claim
16 words
The device set forth in claim 67 wherein said correlator configuration circuitry provides adjacent correlator presumming.
Claim 72
Dependent Claim
17 words
The device set forth in claim 68, wherein said correlator configuration circuitry provides full null zone operation.
Claim 73
Dependent Claim
26 words
The device set forth in claim 59 further including: eighth circuitry means for causing one channel to generate a test signal for use by other channels.
Claim 74
Independent Claim
60 words
A device for use in GPS receivers for processing of multiple digitized satellite signals, said device comprising, on a single integrated circuit: multiple P(Y) and C/A-code channel means for processing said multiple digitized satellite signals; and a search processor for fast signal acquisition, including means for simultaneously searching a plurality of frequency bins in each of said multiple channel means.
Claim 75
Independent Claim
60 words
A device for use in GPS receivers for processing of multiple digitized satellite signals, said device comprising, on a single integrated circuit: multiple P(Y) and C/A-code channel means for processing said multiple digitized satellite signals; and a search processor for fast signal acquisition, including means for simultaneously searching a plurality of frequency bins in each of said multiple channel means.
Claim 76
Dependent Claim
17 words
The device set forth in claim 71 further including: circuitry for selectively processing L1 or L2 signals.
Claim 77
Independent Claim
193 words
A device for tracking and acquiring global positioning system (GPS) signals from multiple satellites, said device comprising, on a single integrated circuit: two P(Y) and C/A-code channels; a search processor for fast signal acquisition; support circuitry means for processing null zone signals; said channels each comprising: a carrier generator; a code clock generator; a P-code generator; a C/A-code generator; eight predetection integration accumulators; and a noise meter; said search processor comprising: a discrete fourier transform circuit; first circuitry means for performing frequency bin interpolation; second circuitry means for implementing a Robertson approximation for envelope calculation; third circuitry means for implementing a Tong detection algorithm to determine if signal is present; a threshold calculator which uses measurements from said noise meter; fourth circuitry means for calculating a second search threshold for the interpolated frequency bins; fifth circuitry means for advancing or retarding code state as required during search; a mush counter which counts Tong detection iterations for a specific code state and either forces a new code state or stops search; and a hit counter which counts hits associated with a specified number of discrete fourier transform cycles and reports the most current value.
Claim 78
Independent Claim
193 words
A device for tracking and acquiring global positioning system (GPS) signals from multiple satellites, said device comprising, on a single integrated circuit: two P(Y) and C/A-code channels; a search processor for fast signal acquisition; support circuitry means for processing null zone signals; said channels each comprising: a carrier generator; a code clock generator; a P-code generator; a C/A-code generator; eight predetection integration accumulators; and a noise meter; said search processor comprising: a discrete fourier transform circuit; first circuitry means for performing frequency bin interpolation; second circuitry means for implementing a Robertson approximation for envelope calculation; third circuitry means for implementing a Tong detection algorithm to determine if signal is present; a threshold calculator which uses measurements from said noise meter; fourth circuitry means for calculating a second search threshold for the interpolated frequency bins; fifth circuitry means for advancing or retarding code state as required during search; a mush counter which counts Tong detection iterations for a specific code state and either forces a new code state or stops search; and a hit counter which counts hits associated with a specified number of discrete fourier transform cycles and reports the most current value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |