Patent US5535231A successfully refreshed from Google Patents.
US5535231A
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US
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Optoelectronic circuit including heterojunction bipolar transistor laser and photodetector
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-11-08
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Granted: 1996-07-09
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Expires: 2014-11-08
Abstract
Abstract An optoelectronic integrated circuit furnishes a monolithic integration of high-speed transistors, lasers and photodetectors for optoelectronic communication applications. The monolithic device integrates an indium phosphorus (InP)/indium gallium arsenide (InGaAs) emitter-down heterojunction bipolar transistor with an InP/InGaAs quantum well laser and modulator, and a metal-semiconductor-metal photodetector.
Inventors
- 👤 Kwyro Lee
- 👤 Michael Shur
- 👤 Stephen H. Jones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:54
CPC Classifications
H; H01; H01S; H01S5/00; H01S5/02; H01S5/026; H01S5/0262; H01S5/0261; H01S5/0264
Claims Analysis
Total Claims: 52
Claim 1
Independent Claim
115 words
A monolithic optoelectronic integrated circuit comprising: an emitter-down heterostructure bipolar transistor having a planar surface and having a buried emitter layer, a surface collector layer separated into a plurality of surface regions and a medial base layer coupled between the emitter layer and the collector layer and having a region extending between collector layer surface regions to the planar surface; a laser overlying and coupled to a first collector surface region of the plurality of collector surface regions; and a metal layer of a metal-semiconductor-metal photodetector overlying and coupled to a portion of the planar surface including part of the first collector surface region, the base layer surface region and a second collector surface region.
Claim 2
Dependent Claim
115 words
A monolithic optoelectronic integrated circuit comprising: an emitter-down heterostructure bipolar transistor having a planar surface and having a buried emitter layer, a surface collector layer separated into a plurality of surface regions and a medial base layer coupled between the emitter layer and the collector layer and having a region extending between collector layer surface regions to the planar surface; a laser overlying and coupled to a first collector surface region of the plurality of collector surface regions; and a metal layer of a metal-semiconductor-metal photodetector overlying and coupled to a portion of the planar surface including part of the first collector surface region, the base layer surface region and a second collector surface region.
Claim 3
Dependent Claim
24 words
A circuit as in claim 1 further comprising: a bias diode coupling the base layer and the emitter layer of the heterostructure bipolar transistor.
Claim 4
Dependent Claim
19 words
A circuit as in claim 1 wherein the heterostructure bipolar transistor furnishes the semiconductor layer of the metal-semiconductor-metal photodetector.
Claim 5
Dependent Claim
38 words
A circuit as in claim 1 wherein the heterostructure bipolar transistor includes: an n-type lightly-doped InGaAs collector in the surface layer; a p-type heavily-doped InGaAs base medial layer; and an n-type heavily-doped InP emitter in the buried layer.
Claim 6
Dependent Claim
145 words
A circuit as in claim 1 wherein the heterostructure bipolar transistor includes: an In 0 .53 Ga 0 .47 As collector lightly-doped with n-type ions to a concentration in the range from approximately 10 16 cm -3 to approximately 10 18 cm -3 and having a thickness in the range from approximately 300 nm to approximately 700 nm; an In 0 .53 Ga 0 .47 As base heavily-doped with p-type ions to a concentration in the range from approximately 10 17 cm -3 to approximately 10 19 cm -3 and having a thickness in the range from approximately 100 nm to approximately 200 nm; and an InP emitter heavily-doped with n-type ions to a concentration in the range from approximately 10 17 cm -3 to approximately 10 18 cm -3 and having a thickness in the range from approximately 200 nm to approximately 400 nm,
Claim 7
Dependent Claim
97 words
A circuit as in claim 1 wherein the heterostructure bipolar transistor includes: an In 0 .53 Ga 0 .47 As collector lightly-doped with n-type ions to a concentration of approximately 10 17 cm -3 and having a thickness of approximately 500 nm; an In 0 .53 Ga 0 .47 As base heavily-doped with p-type ions to a concentration of approximately 2×10 18 cm -3 and having a thickness of approximately 150 nm; and an InP emitter heavily-doped with n-type ions to a concentration of approximately 5×10 17 cm -3 and having a thickness of approximately 300 nm.
Claim 8
Dependent Claim
62 words
A circuit as in claim 1 wherein the laser is a cleaved-cavity multiple quantum well InP/InGaAs structure including: an upper cladding layer; a lower cladding layer; a contact layer coupling the lower cladding layer to the heterostructure bipolar transistor collector; and an active region coupled between the upper and lower cladding layers and having a plurality of alternating InGaAs and InP layers.
Claim 9
Dependent Claim
115 words
A circuit as in claim 7 wherein: the upper cladding layer is a heavily-zinc-doped p-type InP layer having a thickness in the range from 1μ to 10μ; the lower cladding is a heavily-silicon-doped n-type InP layer having a thickness in the range from 0.5μ to 15μ; the contact layer is a SiO 2 insulated Al/Au strip having a thickness in the range from 3μ to 20μ; and the laser active region includes a plurality of eight to sixteen In 0 .53 Ga 0 .47 As layers having a thickness in a range from 3 nm to 20 nm alternating with InP barrier layers having a thickness in the range from 7 nm to 25 nm.
Claim 10
Dependent Claim
93 words
A circuit as in claim 7 wherein: the upper cladding layer is a heavily-zinc-doped p-type InP layer having a thickness of approximately 1.5μ; the lower cladding is a heavily-silicon-doped n-type InP layer having a thickness of approximately 2.5μ; the contact layer is a SiO 2 insulated Al/Au strip having a thickness of approximately 7μ; and the laser active region includes a plurality of eight to sixteen In 0 .53 Ga 0 .47 As layers having a thickness of approximately 7 nm alternating with InP barrier layers having a thickness of approximately 15 nm.
Claim 11
Dependent Claim
34 words
A circuit as in claim 1 wherein the metal-semiconductor-metal photodetector is an interdigitated metal pad having a plurality of detector fingers and fabricated overlying and adjacent to the collector of the heterostructure bipolar transistor.
Claim 12
Dependent Claim
20 words
A circuit as in claim 10 wherein interdigitated metal layer of the metal-semiconductor-metal photodetector is constructed from a Tungsten/Titanium alloy.
Claim 13
Dependent Claim
20 words
A circuit as in claim 10 wherein interdigitated metal layer of the metal-semiconductor-metal photodetector is constructed from a Gold/Germanium/Nickel alloy.
Claim 14
Dependent Claim
14 words
A circuit as in claim 10 wherein interdigitated metal fingers have a circular form.
Claim 15
Dependent Claim
38 words
A circuit as in claim 10 wherein: the metal pad has a thickness in the range from 150μ to 300μ; and the size of the spacing between the detector fingers is in the range from 1μ to 2μ.
Claim 16
Dependent Claim
38 words
A circuit as in claim 1 further comprising: a collector bias terminal coupled to receive a collector bias signal; and a collector load diode coupled from the collector bias terminal to the collector of the heterostructure bipolar transistor.
Claim 17
Dependent Claim
26 words
A circuit as in claim 15 wherein the collector load diode includes a metal pad overlying and adjacent to the collector of the heterostructure bipolar transistor.
Claim 18
Dependent Claim
27 words
A circuit as in claim 1 further comprising a metal-semiconductor-metal bias terminal coupled to the metal pad of the metal-semiconductor-metal photodetector to receive a metal-semiconductor-metal bias signal.
Claim 19
Dependent Claim
29 words
A circuit as in claim 1 further comprising a laser bias terminal coupled to the upper cladding layer of the quantum well laser to receive a laser bias signal.
Claim 20
Dependent Claim
62 words
A monolithic optoelectronic integrated circuit comprising: a heterostructure bipolar transistor having a base, an emitter and a collector; a quantum well laser coupled to the collector of the heterostructure bipolar transistor; and a metal-semiconductor-metal photodetector coupled by an ohmic contact to the base of the heterostructure bipolar transistor and coupled by a Schottky contact to the collector of the heterostructure bipolar transistor.
Claim 21
Dependent Claim
62 words
A monolithic optoelectronic integrated circuit comprising: a heterostructure bipolar transistor having a base, an emitter and a collector; a quantum well laser coupled to the collector of the heterostructure bipolar transistor; and a metal-semiconductor-metal photodetector coupled by an ohmic contact to the base of the heterostructure bipolar transistor and coupled by a Schottky contact to the collector of the heterostructure bipolar transistor.
Claim 22
Dependent Claim
22 words
A circuit as in claim 19 further comprising: a bias diode coupling the base and the emitter of the heterostructure bipolar transistor.
Claim 23
Dependent Claim
46 words
A circuit as in claim 19 wherein the heterostructure bipolar transistor has a three-layer emitter-down structure and includes: an n-type lightly-doped InGaAs collector in the top layer; a p-type heavily-doped InGaAs base in the middle layer; and an n-type heavily-doped InP emitter in the bottom layer.
Claim 24
Dependent Claim
145 words
A circuit as in claim 19 wherein the heterostructure bipolar transistor includes: an In 0 .53 Ga 0 .47 As collector lightly-doped with n-type ions to a concentration in the range from approximately 10 16 Cm -3 to approximately 10 18 cm -3 and having a thickness in the range from approximately 300 nm to approximately 700 nm; an In 0 .53 Ga 0 .47 As base heavily-doped with p-type ions to a concentration in the range from approximately 10 17 cm -3 to approximately 10 10 cm -3 and having a thickness in the range from approximately 100 nm to approximately 200 nm; and an InP emitter heavily-doped with n-type ions to a concentration in the range from approximately 10 17 cm -3 to approximately 10 18 cm -3 and having a thickness in the range from approximately 200 nm to approximately 400 nm.
Claim 25
Dependent Claim
97 words
A circuit as in claim 19 wherein the heterostructure bipolar transistor includes: an In 0 .53 Ga 0 .47 As collector lightly-doped with n-type ions to a concentration of approximately 10 17 cm -3 and having a thickness of approximately 500 nm; an In 0 .53 Ga 0 .47 As base heavily-doped with p-type ions to a concentration of approximately 2×10 18 cm -3 and having a thickness of approximately 150 nm; and an InP emitter heavily-doped with n-type ions to a concentration of approximately 5×10 17 cm -3 and having a thickness of approximately 300 nm,
Claim 26
Dependent Claim
64 words
A circuit as in claim 19 wherein the quantum well laser is a cleaved-cavity multiple quantum well InP/InGaAs structure including: an upper cladding layer; a lower cladding layer; a contact layer coupling the lower cladding layer to the heterostructure bipolar transistor collector; and an active region coupled between the upper and lower cladding layers and having a plurality of alternating InGaAs and InP layers,
Claim 27
Dependent Claim
115 words
A circuit as in claim 24 wherein: the upper cladding layer is a heavily-zinc-doped p-type InP layer having a thickness in the range from 1μ to 10μ; the lower cladding is a heavily-silicon-doped n-type InP layer having a thickness in the range from 0.5μ to 15μ; the contact layer is a SiO 2 insulated Al/Au strip having a thickness in the range from 3μ to 20μ; and the laser active region includes a plurality of eight to sixteen In 0 .53 Ga 0 .47 As layers having a thickness in a range from 3 nm to 20 nm alternating with InP barrier layers having a thickness in the range from 7 nm to 25 nm.
Claim 28
Dependent Claim
93 words
A circuit as in claim 24 wherein: the upper cladding layer is a heavily-zinc-doped p-type InP layer having a thickness of approximately 1.5μ; the lower cladding is a heavily-silicon-doped n-type InP layer having a thickness of approximately 2.5μ; the contact layer is a SiO 2 insulated Al/Au strip having a thickness of approximately 7μ; and the laser active region includes a plurality of eight to sixteen In 0 .53 Ga 0 .47 As layers having a thickness of approximately 7 nm alternating with InP barrier layers having a thickness of approximately 15 nm.
Claim 29
Dependent Claim
34 words
A circuit as in claim 19 wherein the metal-semiconductor-metal photodetector is an interdigitated metal pad having a plurality of detector fingers and fabricated overlying and adjacent to the collector of the heterostructure bipolar transistor.
Claim 30
Dependent Claim
20 words
A circuit as in claim 27 wherein interdigitated metal layer of the metal-semiconductor-metal photodetector is constructed from a Tungsten/Titanium alloy.
Claim 31
Dependent Claim
20 words
A circuit as in claim 27 wherein interdigitated metal layer of the metal-semiconductor-metal photodetector is constructed from a Gold/Germanium/Nickel alloy.
Claim 32
Dependent Claim
14 words
A circuit as in claim 27 wherein interdigitated metal fingers have a circular form.
Claim 33
Dependent Claim
38 words
A circuit as in claim 27 wherein: the metal pad has a thickness in the range from 150μ to 300μ; and the size of the spacing between the detector fingers is in the range from 1μ to 2μ.
Claim 34
Dependent Claim
38 words
A circuit as in claim 19 further comprising: a collector bias terminal coupled to receive a collector bias signal; and a collector load diode coupled from the collector bias terminal to the collector of the heterostructure bipolar transistor.
Claim 35
Dependent Claim
26 words
A circuit as in claim 32 wherein the collector load diode includes a metal pad overlying and adjacent to the collector of the heterostructure bipolar transistor.
Claim 36
Dependent Claim
27 words
A circuit as in claim 19 further comprising a metal-semiconductor-metal bias terminal coupled to the metal pad of the metal-semiconductor-metal photodetector to receive a metal-semiconductor-metal bias signal.
Claim 37
Dependent Claim
29 words
A circuit as in claim 19 further comprising a laser bias terminal coupled to the upper cladding layer of the quantum well laser to receive a laser bias signal.
Claim 38
Dependent Claim
117 words
A monolithic optoelectronic integrated circuit comprising: an emitter-down heterostructure bipolar transistor having a planar surface and having a buried emitter layer, a surface collector layer separated into a plurality of surface regions and a medial base layer coupled between the emitter layer and the collector layer and having a region extending between collector layer surface regions to the planar surface; and a metal layer of a metal-semiconductor-metal photodetector, a semiconductor region of the photodetector being supplied by the semiconductor layers of the heterostructure bipolar transistor, the metal layer overlying and coupled to a portion of the planar surface including part of the first collector surface region, the base layer surface region and a second collector surface region.
Claim 39
Dependent Claim
117 words
A monolithic optoelectronic integrated circuit comprising: an emitter-down heterostructure bipolar transistor having a planar surface and having a buried emitter layer, a surface collector layer separated into a plurality of surface regions and a medial base layer coupled between the emitter layer and the collector layer and having a region extending between collector layer surface regions to the planar surface; and a metal layer of a metal-semiconductor-metal photodetector, a semiconductor region of the photodetector being supplied by the semiconductor layers of the heterostructure bipolar transistor, the metal layer overlying and coupled to a portion of the planar surface including part of the first collector surface region, the base layer surface region and a second collector surface region.
Claim 40
Dependent Claim
24 words
A circuit as in claim 36 further comprising: a bias diode coupling the base layer and the emitter layer of the heterostructure bipolar transistor.
Claim 41
Dependent Claim
38 words
A circuit as in claim 36 wherein the heterostructure bipolar transistor includes: an n-type lightly-doped InGaAs collector in the surface layer; a p-type heavily-doped InGaAs base medial layer; and an n-type heavily-doped InP emitter in the buried layer.
Claim 42
Dependent Claim
144 words
A circuit as in claim 36 wherein the heterostructure bipolar transistor includes: an In 0 .53 Ga 0 .47 As collector lightly-doped with n-type ions to a concentration in the range from approximately 10 16 cm -3 to approximately 10 18 cm -3 and having a thickness in the range from approximately 300 nm to approximately 700 nm; an In 0 .53 Ga 0 .47 base heavily-doped with p-type ions to a concentration in the range from approximately 10 17 cm -3 to approximately 10 19 cm -3 and having a thickness in the range from approximately 100 nm to approximately 200 nm; and an InP emitter heavily-doped with n-type ions to a concentration in the range from approximately 10 17 cm -3 to approximately 10 18 cm -3 and having a thickness in the range from approximately 200 nm to approximately 400 nm.
Claim 43
Dependent Claim
97 words
A circuit as in claim 36 wherein the heterostructure bipolar transistor includes: an In 0 .53 Ga 0 .47 As collector lightly-doped with n-type ions to a concentration of approximately 10 17 cm -3 and having a thickness of approximately 500 nm; an In 0 .53 Ga 0 .47 As base heavily-doped with p-type ions to a concentration of approximately 2×10 18 cm -3 and having a thickness of approximately 150 nm; and an InP emitter heavily-doped with n-type ions to a concentration of approximately 5×10 17 cm -3 and having a thickness of approximately 300 nm.
Claim 44
Dependent Claim
34 words
A circuit as in claim 36 wherein the metal-semiconductor-metal photodetector is an interdigitated metal pad having a plurality of detector fingers and fabricated overlying and adjacent to the collector of the heterostructure bipolar transistor.
Claim 45
Dependent Claim
20 words
A circuit as in claim 41 wherein interdigitated metal layer of the metal-semiconductor-metal photodetector is constructed from a Tungsten/Titanium alloy.
Claim 46
Dependent Claim
20 words
A circuit as in claim 41 wherein interdigitated metal layer of the metal-semiconductor-metal photodetector is constructed from a Gold/Germanium/Nickel alloy.
Claim 47
Dependent Claim
14 words
A circuit as in claim 41 wherein interdigitated metal fingers have a circular form.
Claim 48
Dependent Claim
38 words
A circuit as in claim 44 wherein: the metal pad has a thickness in the range from 150μ to 300μ; and the size of the spacing between the detector fingers is in the range from 1μ to 2μ.
Claim 49
Dependent Claim
38 words
A circuit as in claim 36 further comprising: a collector bias terminal coupled to receive a collector bias signal; and a collector load diode coupled from the collector bias terminal to the collector of the heterostructure bipolar transistor.
Claim 50
Dependent Claim
26 words
A circuit as in claim 46 wherein the collector load diode includes a metal pad overlying and adjacent to the collector of the heterostructure bipolar transistor.
Claim 51
Dependent Claim
27 words
A circuit as in claim 36 further comprising a metal-semiconductor-metal bias terminal coupled to the metal pad of the metal-semiconductor-metal photodetector to receive a metal-semiconductor-metal bias signal.
Claim 52
Dependent Claim
29 words
A circuit as in claim 36 further comprising a laser bias terminal coupled to the upper cladding layer of the quantum well laser to receive a laser bias signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |