Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: an EEPROM memory cell array comprising a plurality of memory cells disposed in a matrix, each memory cell including a non-volatile memory transistor for electrically writing and erasing data; means for generating a high voltage required to write data into and erase data from said memory cell array; means for selectively supplying the high voltage to a memory cell; and means for controlling said means for generating and said means for selectively supplying to control writing data into, reading data from, and erasing data from the memory cell array, said means for selectively supplying the high voltage to a memory cell including a plurality of switches, each switch having: a selection transistor; a plurality of charge pump transistors, each charge pump transistor having a drain and a gate connected to each other, at least one of the charge pump transistors being connected to said selection transistor; and a plurality of capacitors, wherein said plurality of charge pump transistors and said plurality of capacitors form a multi-stage charge pump.

Claim 3

A semiconductor integrated circuit comprising: an EEPROM memory cell array comprising a plurality of memory cells disposed in a matrix, each memory cell including a non-volatile memory transistor for electrically writing and erasing data; means for generating a high voltage required to write data into and erase data from said memory cell array; means for selectively supplying the high voltage to a memory cell; and means for controlling said means for generating and said means for selectively supplying to control writing data into, reading data from, and erasing data from the memory cell array, said means for selectively supplying the high voltage to a memory cell including: a selection transistor; a charge pump transistor having a drain and a gate connected to each other; and a capacitor, said charge pump transistor and said capacitor forming a charge pump, said selection transistor being coupled to the charge pump, threshold voltages of said selection transistor and said charge pump transistor being different, with the threshold voltage of said charge pump transistor being lower than the threshold voltage of said selection transistor.

Claim 4

A semiconductor integrated circuit comprising: an EEPROM memory cell array comprising a plurality of memory cells disposed in a matrix, each memory cell including a non-volatile memory transistor for electrically writing and erasing data; means for generating a high voltage required to write data into and erase data from said memory cell array; means for selectively supplying the high voltage to a memory cell; and means for controlling said means for generating and said means for selectively supplying to control writing data into, reading data from, and erasing data from the memory cell array, said means for selectively supplying the high voltage to a memory cell including: a selection transistor; a charge pump transistor having a drain and a gate connected to each other; and a capacitor, said charge pump transistor and said capacitor forming a charge pump, said selection transistor being coupled to the charge pump, threshold voltages of said selection transistor and said charge pump transistor being different, with the threshold voltage of said charge pump transistor being lower than the threshold voltage of said selection transistor.

Claim 5

A semiconductor integrated circuit comprising: an EEPROM memory cell array comprising a plurality of memory cells disposed in a matrix, each memory cell including a non-volatile memory transistor for electrically writing and erasing data; means for generating a high voltage required to write data into and erase data from said memory cell array; means for selectively supplying the high voltage to a memory cell; and means for controlling said means for generating and said means for selectively supplying to control writing data into, reading data from, and erasing data from the memory cell array, said means for selectively supplying the high voltage to a memory cell including: a selection transistor; a plurality of charge pump transistors, each charge pump transistor having a drain and a gate connected to each other, at least one charge pump transistor being connected to said selection transistor; and a plurality of capacitors, said plurality of charge pump transistors and said plurality of capacitors forming a multi-stage charge pump, threshold voltages of said selection transistors and said charge pump transistors being different, with the threshold voltages of said charge pump transistors being lower than the threshold voltages of said selection transistors.

Claim 6

A semiconductor integrated circuit comprising: an EEPROM memory cell array comprising a plurality of memory cells disposed in a matrix, each memory cell including a non-volatile memory transistor for electrically writing and erasing data; means for generating a high voltage required to write data into and erase data from said memory cell array; means for selectively supplying the high voltage to a memory cell; and means for controlling said means for generating and said means for selectively supplying to control writing data into, reading data from, and erasing data from the memory cell array, said means for selectively supplying the high voltage to a memory cell including: a selection transistor; a plurality of charge pump transistors, each charge pump transistor having a drain and a gate connected to each other, at least one charge pump transistor being connected to said selection transistor; and a plurality of capacitors, said plurality of charge pump transistors and said plurality of capacitors forming a multi-stage charge pump, threshold voltages of said selection transistors and said charge pump transistors being different, with the threshold voltages of said charge pump transistors being lower than the threshold voltages of said selection transistors.