SRAM cell having load thin film transistors

Claim 2

A static random access memory device comprising: first and second power supply lines; a word line; first and second bit lines; first and second nodes; a first load thin film transistor connected between said first power supply line and said first node and having a gate electrode connected to said second node; a second load thin film transistor connected between said first power supply line and said second node and having a gate electrode connected to said first node; a first drive bulk transistor connected between said first node and said second power supply line and having a gate electrode connected to said second node; a second drive bulk transistor connected between said second node and said second power supply line and having a gate electrode connected to said first node; a first transfer bulk transistor connected between said first bit line and said first node and having a gate electrode connected to said word line; and a second transfer bulk transistor connected between said second bit line and said second node and having a gate electrode connected to said word line, said second bit line being arranged in the proximity of said first load thin film transistor to create a first parasitic load thin film transistor, said first bit line being arranged in the proximity of said second load thin film transistor to create a second parasitic load thin film transistor.

Claim 3

A device as set forth in claim 1, wherein said second bit line is located in an opposite side of said gate electrode of said first load thin film transistor in respect to a source-channel-drain layer thereof, said first bit line being located in an opposite side of said gate electrode of said second load thin film transistor in respect to a source-channel-drain layer thereof.

Claim 4

A static random access memory device comprising: first and second power supply lines; first and second word lines to which the same potential is applied; first and second bit lines; first and second nodes; a first load thin film transistor connected between said first power supply line and said first node and having a gate electrode connected to said second node; a second load thin film transistor connected between said first power supply line and said second node and having a gate electrode connected to said first node; a first drive bulk transistor connected between said first node and said second power supply line and having a gate electrode connected to said second node; a second drive bulk transistor connected between said second node and said second power supply line and having a gate electrode connected to said first node; a first transfer bulk transistor connected between said first bit line and said first node and having a gate electrode connected to said first word line; and a second transfer bulk transistor connected between said second bit line and said second node and having a gate electrode connected to said second word line, said second bit line being arranged in the proximity of said first load thin film transistor to create a first parasitic load thin film transistor, said first bit line being arranged in the proximity of said second load thin film transistor to create a second parasitic load thin film transistor.

Claim 5

A static random access memory device comprising: first and second power supply lines; first and second word lines to which the same potential is applied; first and second bit lines; first and second nodes; a first load thin film transistor connected between said first power supply line and said first node and having a gate electrode connected to said second node; a second load thin film transistor connected between said first power supply line and said second node and having a gate electrode connected to said first node; a first drive bulk transistor connected between said first node and said second power supply line and having a gate electrode connected to said second node; a second drive bulk transistor connected between said second node and said second power supply line and having a gate electrode connected to said first node; a first transfer bulk transistor connected between said first bit line and said first node and having a gate electrode connected to said first word line; and a second transfer bulk transistor connected between said second bit line and said second node and having a gate electrode connected to said second word line, said second bit line being arranged in the proximity of said first load thin film transistor to create a first parasitic load thin film transistor, said first bit line being arranged in the proximity of said second load thin film transistor to create a second parasitic load thin film transistor.

Claim 6

A device as set forth in claim 3, wherein said second bit line is located in an opposite side of said gate electrode of said first load thin film transistor in respect to a source-channel-drain layer thereof, said first bit line being located in an opposite side of said gate electrode of said second load thin film transistor in respect to a source-channel-drain layer thereof.

Claim 7

A device as set forth in claim 3, wherein said first and second word lines, said first and second bit lines, said first and second thin film transistors, said first and second drive bulk transistors, and said first second transfer bulk transistors are symmetrical with respect to one center of symmetry.

Claim 8

A static random access memory device including a flip-flop having first and second load thin film transistors whose drains are connected via first and second transfer bulk transistors to first and second bit lines, respectively, wherein said second bit line is arranged over said first load thin film transistor, and said first bit line is arranged over said second thin film transistor.

Claim 9

A static random access memory device including a flip-flop having first and second load thin film transistors whose drains are connected via first and second transfer bulk transistors to first and second bit lines, respectively, wherein said second bit line is arranged over said first load thin film transistor, and said first bit line is arranged over said second thin film transistor.

Claim 10

A static random access memory device including a flip-flop having first and second load thin film transistors whose drains are connected via first and second transfer bulk transistors to first and second bit lines, respectively, wherein a gate electrode of said first load thin film transistor is located beneath a channel region of said first load thin film transistor, and said second bit line is located over said channel region of said first load thin film transistor, and wherein a gate electrode of said second load thin film transistor is located beneath a channel region of said second load thin film transistor, and said first bit line is located over said channel region of said second load thin film transistor.

Claim 11

A static random access memory device including a flip-flop having first and second load thin film transistors whose drains are connected via first and second transfer bulk transistors to first and second bit lines, respectively, wherein a gate electrode of said first load thin film transistor is located beneath a channel region of said first load thin film transistor, and said second bit line is located over said channel region of said first load thin film transistor, and wherein a gate electrode of said second load thin film transistor is located beneath a channel region of said second load thin film transistor, and said first bit line is located over said channel region of said second load thin film transistor.