Patent US5535153A successfully refreshed from Google Patents.
US5535153A
Expired / Lapsed
US
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Semiconductor device
Assignee: Renesas Electronics Corp
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Filing: 1994-10-13
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Granted: 1996-07-09
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Expires: 2014-10-13
Abstract
Abstract A semiconductor device has a plurality of cell arrays each comprising a plurality of memory cells each composed of an MIS transistor and a capacitor formed from a conductive layer, a plurality of word lines and bit lines intersecting each other at the memory cells, a plurality of sense amplifiers alternating with the cell arrays, a plurality of row decoders, a plurality of column decoders, each of the column decoders being connected to and shared by a plurality of the sense amplifiers, and a plurality of interconnections for transmitting selective signals from the word lines, the bit lines and the column decoders. The interconnections for transmitting selective signals from the bit lines and the column decoders extend in the direction in which the cell arrays and the sense amplifiers are arrayed. The interconnections for transmitting selective signals from the word lines, the bit lines and the column decoders are formed from three different layers, other than the conductive layer for forming a capacitor, on the cell arrays. The interconnections for transmitting selective signals from the column decoders are formed from a metallic layer on the cell arrays.
Inventors
- 👤 Takanori Saeki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:18
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
208 words
A semiconductor device comprising: a plurality of cell arrays each comprising a plurality of memory cells each composed of a Metal Insulator Semiconductor transistor and a capacitor formed by a conductive layer; a plurality of word lines and bit lines which intersect each other at said memory cells; a plurality of sense amplifiers alternating with said cell arrays; a plurality of column decoders, each of said column decoders being connected to and shared by a plurality of said sense amplifiers; and a plurality of interconnections for transmitting selective signals from said word lines, said bit lines, and said column decoders, said interconnections for transmitting selective signals from said bit lines and said column decoders extending in a direction in which said cell arrays and said sense amplifiers are arrayed, said interconnections for transmitting selective signals from said word lines, said bit lines, and said column decoders being formed from four different layers, including said conductive layer for forming said capacitor, on the semiconductor device; wherein, said interconnections for transmitting selective signals from said column decoders are formed from a metallic layer on the cell arrays and are formed from a conductive layer, which is the same layer that forms plate electrodes of the capacitors, on the sense amplifiers.
Claim 2
Dependent Claim
208 words
A semiconductor device comprising: a plurality of cell arrays each comprising a plurality of memory cells each composed of a Metal Insulator Semiconductor transistor and a capacitor formed by a conductive layer; a plurality of word lines and bit lines which intersect each other at said memory cells; a plurality of sense amplifiers alternating with said cell arrays; a plurality of column decoders, each of said column decoders being connected to and shared by a plurality of said sense amplifiers; and a plurality of interconnections for transmitting selective signals from said word lines, said bit lines, and said column decoders, said interconnections for transmitting selective signals from said bit lines and said column decoders extending in a direction in which said cell arrays and said sense amplifiers are arrayed, said interconnections for transmitting selective signals from said word lines, said bit lines, and said column decoders being formed from four different layers, including said conductive layer for forming said capacitor, on the semiconductor device; wherein, said interconnections for transmitting selective signals from said column decoders are formed from a metallic layer on the cell arrays and are formed from a conductive layer, which is the same layer that forms plate electrodes of the capacitors, on the sense amplifiers.
Claim 3
Dependent Claim
128 words
A semiconductor device according to claim 1, wherein said four different layers include a first layer which provides gate electrodes of the MIS transistors, comprises a laminated layer of polycrystalline silicon and silicide, and has a portion providing said word lines; a second layer which comprises a silicide layer and has a portion providing said bit lines; a third layer which comprises a metallic layer and has a portion providing the interconnections on the cell arrays for transmitting selective signals from said column decoders; and a fourth layer which comprises a conductive layer, which is the same layer that forms plate electrodes of the capacitors, on the sense amplifiers and has a portion providing the interconnections on the cell arrays for transmitting selective signals from said column decoders.
Claim 4
Dependent Claim
135 words
A semiconductor device according to claim 1, wherein said four different layers include a first layer which provides gate electrodes of the MIS transistors, which comprises a laminated layer of polycrystalline silicon and silicide, and has a portion providing said word lines; a second layer which comprises a laminated layer of polycrystalline silicon and silicide and has a portion providing said bit lines; and a third layer which comprises a metallic layer and has a portion providing the interconnections on the cell arrays for transmitting selective signals from said column decoders; and a fourth layer which comprises a conductive layer, which is the same layer that forms plate electrodes of the capacitors, on the sense amplifiers and has a portion providing the interconnections on the cell arrays for transmitting selective signals from said column decoders.
References Cited (Backward Citations)
US5361233A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |