Circuit for controlling bias voltage used to regulate contrast in a display panel

Claim 2

A circuit for controlling a bias voltage used to regulate contrast in a video display system capable of operating in a plurality of modes, the circuit comprising: means for detecting a video mode of the video display system; means for generating a pulse width modulated signal having a duty cycle, wherein said duty cycle is varied based on said detected video mode, including: a register for storing a base contrast value; a register for storing a first offset contrast value; means responsive to said detected video mode for selectively combining said base and first offset contrast values to produce a final contrast value, wherein said base and first offset contrast values are combined for a first video mode and said base contrast value is used alone for a second video mode; and means responsive to said final contrast value for producing said pulse width modulated signal, wherein said duty cycle of said pulse width modulated signal is proportional to said final contrast value; and means for converting said pulse width modulated signal to the bias voltage, wherein the bias voltage is proportional to the duty cycle of said pulse width modulated signal.

Claim 3

The circuit of claim 1, wherein said generating means further includes a register for storing a second offset contrast value, and wherein said means for selectively combining further combines said base and second offset contrast values for a third video mode to produce a final contrast value.

Claim 4

The circuit of claim 1, wherein said means for producing said pulse width modulated signal includes: a counter having a counter output value; and means for comparing said final contrast value and said counter value and providing a signal in a first state when said counter value is less than said final contrast value and in a second state when said counter value is greater than said final contrast value, said signal forming said pulse width modulated signal.

Claim 5

The circuit of claim 1, wherein said means for selectively combining performs an arithmetic function on said base and first offset contrast values to produce said final contrast value.

Claim 6

The circuit of claim 1, wherein said means for converting said pulse width modulated signal to the bias voltage includes: an averaging filter receiving a version of said pulse width modulated signal and producing an output signal representative of the average DC level of said pulse width modulated signal; and a voltage regulator receiving said averaging filter output signal and providing the bias voltage as an output.

Claim 7

The circuit of claim 5, wherein said means for converting said pulse width modulated signal to the bias voltage further includes: a thermistor located to monitor the temperature of the video display, said thermistor connected to said voltage regulator to adjust the bias voltage to compensate for temperature changes.

Claim 8

A video display system for controlling a bias voltage used to regulate contrast of a video display, the video display system capable of operating in a plurality of modes, the system comprising: a video controller including: a mode register for storing the video display mode of the video controller; means for detecting a video mode of the video controller as contained in said mode register; means for generating a pulse width modulated signal having a duty cycle, wherein said duty cycle is varied based on said detected video mode, including: a register for storing a base contrast value; a register for storing a first offset contrast value; means responsive to said detected video mode for selectively combining said base and first offset contrast values to produce a final contrast value, wherein said base and first offset contrast values are combined for a first video mode and said base contrast value is used alone for a second video mode; and means responsive to said final contrast value for producing said pulse width modulated signal, wherein said duty cycle of said pulse width modulated signal is proportional to said final contrast value; and means for converting said pulse width modulated signal to the bias voltage, wherein the bias voltage is proportional to the duty cycle of said pulse width modulated signal.

Claim 9

A video display system for controlling a bias voltage used to regulate contrast of a video display, the video display system capable of operating in a plurality of modes, the system comprising: a video controller including: a mode register for storing the video display mode of the video controller; means for detecting a video mode of the video controller as contained in said mode register; means for generating a pulse width modulated signal having a duty cycle, wherein said duty cycle is varied based on said detected video mode, including: a register for storing a base contrast value; a register for storing a first offset contrast value; means responsive to said detected video mode for selectively combining said base and first offset contrast values to produce a final contrast value, wherein said base and first offset contrast values are combined for a first video mode and said base contrast value is used alone for a second video mode; and means responsive to said final contrast value for producing said pulse width modulated signal, wherein said duty cycle of said pulse width modulated signal is proportional to said final contrast value; and means for converting said pulse width modulated signal to the bias voltage, wherein the bias voltage is proportional to the duty cycle of said pulse width modulated signal.

Claim 10

The system of claim 7, wherein said generating means further includes a register for storing a second offset contrast value, and wherein said means for selectively combining further combines said base and second offset contrast values for a third video mode to produce a final contrast value.

Claim 11

The system of claim 7, wherein said means for producing said pulse width modulated signal includes: a counter having a counter output value; and means for comparing said final contrast value and said counter value and providing a signal in a first state when said counter value is less than said final contrast value and in a second state when said counter value is greater than said final contrast value, said signal forming said pulse width modulated signal.

Claim 12

The system of claim 7, wherein said means for selectively combining performs an arithmetic function on said base and first offset contrast values to produce said final contrast value.

Claim 13

The system of claim 7, wherein said means for converting said pulse width modulated signal to the bias voltage includes: an averaging filter receiving a version of said pulse width modulated signal and producing an output signal representative of the average DC level of said pulse width modulated signal; and a voltage regulator receiving said averaging filter output signal and providing the bias voltage as an output.

Claim 14

The system of claim 11, wherein said means for converting said pulse width modulated signal to the bias voltage further includes: a thermistor located to monitor the temperature of the video display, said thermistor connected to said voltage regulator to adjust the bias voltage to compensate for temperature changes.

Claim 15

A computer system, comprising: a liquid crystal display panel which receives a bias voltage input to control contrast; a video controller providing video a to said liquid crystal display panel, having a plurality of modes and including: a mode register for storing the video display mode of the video controller; means for detecting a video mode of the video controller from said mode register; and means for generating a pulse width modulated signal having a duty cycle, wherein said duty cycle is varied based on said detected video mode including: a register for storing a base contrast value; a register for storing a first offset contrast value; means responsive to said detected video mode for selectively combining said base and first offset contrast values to produce a final contrast value, wherein said base and first offset contrast values are combined for a first video mode and said base contrast value is used alone for a second video mode; and means responsive to said final contrast value for producing said pulse width modulated signal, wherein said duty cycle of said pulse width modulated signal is proportional to said final contrast value; and means for converting said pulse width modulated signal to the bias voltage, wherein the bias voltage is proportional to the duty cycle of said pulse width modulated signal.

Claim 16

A computer system, comprising: a liquid crystal display panel which receives a bias voltage input to control contrast; a video controller providing video a to said liquid crystal display panel, having a plurality of modes and including: a mode register for storing the video display mode of the video controller; means for detecting a video mode of the video controller from said mode register; and means for generating a pulse width modulated signal having a duty cycle, wherein said duty cycle is varied based on said detected video mode including: a register for storing a base contrast value; a register for storing a first offset contrast value; means responsive to said detected video mode for selectively combining said base and first offset contrast values to produce a final contrast value, wherein said base and first offset contrast values are combined for a first video mode and said base contrast value is used alone for a second video mode; and means responsive to said final contrast value for producing said pulse width modulated signal, wherein said duty cycle of said pulse width modulated signal is proportional to said final contrast value; and means for converting said pulse width modulated signal to the bias voltage, wherein the bias voltage is proportional to the duty cycle of said pulse width modulated signal.

Claim 17

The computer system of claim 13, wherein said generating means further includes a register for storing a second offset contrast value, and wherein said means for selectively combining further combines said base and second offset contrast values for a third video mode to produce a final contrast value.

Claim 18

The computer system of claim 13, wherein said means for producing said pulse width modulated signal includes: a counter having a counter output value; and means for comparing said final contrast value and said counter value and providing a signal in a first state when said counter value is less than said final contrast value and in a second state when said counter value is greater than said final contrast value, said signal forming said pulse width modulated signal.

Claim 19

The computer system of claim 13, wherein said means for selectively combining performs an arithmetic function on said base and first offset contrast values to produce said final contrast value.

Claim 20

The computer system of claim 13, wherein said means for converting said pulse width modulated signal to the bias voltage includes: an averaging filter receiving a version of said pulse width modulated signal and producing an output signal representative of the average DC level of said pulse width modulated signal; and a voltage regulator receiving said averaging filter output signal and providing the bias voltage as an output.

Claim 21

The computer system of claim 17, wherein said means for converting said pulse width modulated signal to the bias voltage further includes: a thermistor located to monitor the temperature of the liquid crystal display, said thermistor connected to said voltage regulator to adjust the bias voltage to compensate for temperature changes.

Claim 24

The method of claim 19, wherein said generating step further includes the step of storing a second offset contrast value, and wherein said step of selectively combining further combines said base and second offset contrast values for a third video mode to produce a final contrast value.

Claim 25

The method of claim 19, wherein said step of producing said pulse width modulated signal includes the steps of: counting in a cyclic fashion; and comparing said final contrast value and said cyclic count value and providing a signal in a first state when said cyclic count value is less than said final contrast value and in a second state when said cyclic count value is greater than said final contrast value, said signal forming said pulse width modulated signal.

Claim 26

The method of claim 19, wherein said step of selectively combining performs an arithmetic function on said base and first offset contrast values to produce said final contrast value.

Claim 27

The method of claim 19, wherein said step of converting said pulse width modulated signal to the bias voltage includes the steps of: averaging the said pulse width modulated signal and producing an output signal representative of the average DC level of said pulse width modulated signal; and providing a regulated signal as the bias voltage, said regulated signal based on said averaged output signal.

Claim 28

The method of claim 23, wherein said step of converting said pulse width modulated signal to the bias voltage further includes the step of monitoring the temperature of the video display and adjusting the bias voltage to compensate for temperature changes.