Patent US5534793A successfully refreshed from Google Patents.
US5534793A
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Parallel antifuse routing scheme (PARS) circuit and method for field programmable gate arrays
Assignee: Texas Instruments Inc
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Filing: 1995-01-24
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Granted: 1996-07-09
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Expires: 2015-01-24
Abstract
Abstract The parallel antifuse scheme may be applied to a field programmable gate array architecture (10) having a logic module (16) with an output coupled to an output track (34, 54, 114, 144, 178, 198) coupled via a cross antifuse (38, 58, 116, 184, 208) to an connecting track (36, 56, 64, 118, 154, 182, 205, 206). The connecting track is further coupled via at least one cross antifuse (44, 46, 72, 74, 120, 122, 160, 162, 190, 218, 220) to at least one input track (40, 42, 68, 70, 188, 214, 216) coupled to an input of at least one logic module. The circuit includes a compensation track (124, 150, 180, 200) running generally in parallel with the output track and at least one parallel antifuse (125, 158, 186, 212) programmably coupling the compensation track (124, 150, 180, 200) and the connecting track. One or more controllable switch (130, 152, 174, 176, 194, 196), such as a pass transistor, is coupled between the output track and the compensation track.
Inventors
- 👤 Mitra Nasserbakht
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17704
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
98 words
A field programmable gate array architecture having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via at least one cross antifuse to at least one input track coupled to an input of at least one logic module, comprising: a compensation track running generally parallel with said output track; a parallel antifuse programmably coupling said compensation track and said connecting track; and a controllable switch coupled between said output track and said compensation track, wherein said controllable switch is an n-channel transistor.
Claim 2
Dependent Claim
98 words
A field programmable gate array architecture having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via at least one cross antifuse to at least one input track coupled to an input of at least one logic module, comprising: a compensation track running generally parallel with said output track; a parallel antifuse programmably coupling said compensation track and said connecting track; and a controllable switch coupled between said output track and said compensation track, wherein said controllable switch is an n-channel transistor.
Claim 3
Dependent Claim
26 words
The field programmable gate array, as set forth in claim 1, wherein said controllable switch is an n-channel transistor having a gate receiving a control signal.
Claim 4
Dependent Claim
105 words
A field programmable gate array architecture having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via at least one cross antifuse to at least one input track coupled to an input of at least one logic module, comprising: a compensation track running generally parallel with said output track; a parallel antifuse programmably coupling said compensation track and said connecting track; and a controllable switch coupled between said output track and said compensation track, wherein said controllable switch closes after said cross antifuse and said parallel antifuse are programmed.
Claim 5
Dependent Claim
105 words
A field programmable gate array architecture having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via at least one cross antifuse to at least one input track coupled to an input of at least one logic module, comprising: a compensation track running generally parallel with said output track; a parallel antifuse programmably coupling said compensation track and said connecting track; and a controllable switch coupled between said output track and said compensation track, wherein said controllable switch closes after said cross antifuse and said parallel antifuse are programmed.
Claim 6
Dependent Claim
109 words
A field programmable gate array architecture having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via at least one cross antifuse to at least one input track coupled to an input of at least one logic module, comprising: a compensation track running generally parallel with said output track; a parallel antifuse coupled between said compensation track and said connecting track; a first controllable switch coupled between said output of said logic module and said output track; a second controllable switch coupled between said output of said logic module and said compensation track.
Claim 7
Dependent Claim
109 words
A field programmable gate array architecture having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via at least one cross antifuse to at least one input track coupled to an input of at least one logic module, comprising: a compensation track running generally parallel with said output track; a parallel antifuse coupled between said compensation track and said connecting track; a first controllable switch coupled between said output of said logic module and said output track; a second controllable switch coupled between said output of said logic module and said compensation track.
Claim 8
Dependent Claim
21 words
The field programmable gate array, as set forth in claim 4, wherein said first and second controllable switches are n-channel transistors.
Claim 9
Dependent Claim
35 words
The field programmable gate array, as set forth in claim 4, wherein said first and second controllable switches are first and second n-channel transistors each having a gate receiving first and second control signals respectively.
Claim 10
Dependent Claim
29 words
The field programmable gate array, as set forth in claim 4, wherein said first and second controllable switches close after said cross antifuse and said parallel antifuse are programmed.
Claim 11
Dependent Claim
40 words
The field programmable gate array, as set forth in claims 4, wherein said output track is substantially vertical, said compensation track is substantially vertical, said connecting track is substantially horizontal, and said at least one input track is substantially vertical.
Claim 12
Dependent Claim
119 words
A parallel antifuse method for a field programmable gate array having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via at least one cross antifuse to at least one input track coupled to an input of at least one logic module, the method comprising the steps of: providing a compensation track running generally parallel with said output track; programmably coupling said compensation track and said connecting track with a programmable parallel antifuse; and providing a controllable switch coupled between said output track and said compensation track, wherein the step of providing the controllable switch includes the step of providing an n-channel transistor.
Claim 13
Dependent Claim
119 words
A parallel antifuse method for a field programmable gate array having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via at least one cross antifuse to at least one input track coupled to an input of at least one logic module, the method comprising the steps of: providing a compensation track running generally parallel with said output track; programmably coupling said compensation track and said connecting track with a programmable parallel antifuse; and providing a controllable switch coupled between said output track and said compensation track, wherein the step of providing the controllable switch includes the step of providing an n-channel transistor.
Claim 14
Dependent Claim
119 words
A parallel antifuse method for a field programmable gate array having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via least one cross antifuse to at least one input track coupled to an input of at least one logic module, the method comprising the steps of: providing a compensation track running generally parallel with said output track; programmably coupling said compensation track and said connecting track with a programmable parallel antifuse; and providing a controllable switch coupled between said output track and said compensation track; opening said controllable switch; programming said cross antifuse and said parallel antifuse; and closing said controllable switch.
Claim 15
Dependent Claim
119 words
A parallel antifuse method for a field programmable gate array having a logic module with an output coupled to an output track coupled via a cross antifuse to an connecting track, said connecting track being coupled via least one cross antifuse to at least one input track coupled to an input of at least one logic module, the method comprising the steps of: providing a compensation track running generally parallel with said output track; programmably coupling said compensation track and said connecting track with a programmable parallel antifuse; and providing a controllable switch coupled between said output track and said compensation track; opening said controllable switch; programming said cross antifuse and said parallel antifuse; and closing said controllable switch.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |