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US5533185A Expired / Lapsed US ⏱️ 0.0 years remaining

Pixel modification unit for use as a functional unit in a superscalar microprocessor

Assignee: Samsung Electronics Co Ltd
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Filing: 1993-10-28
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Granted: 1996-07-02
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Expires: 2013-10-28
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Abstract

Abstract A pixel modification unit is provided for carrying out a variety of raster graphic manipulations in a RISC graphics processor. The pixel modification unit comprises a logic function unit, a masking unit, and a byte mirror unit. The logic function unit can perform any of 16 different logic operations between each bit of a source operand and a destination operand. The source operand may be a bit map fixed data, while the destination operand is pixel data in the bit map corresponding to the graphics image to be modified. The masking unit can mask any or all bits of a destination operand so that the logic function unit does not operate on the masked bits. When masking is implemented, the output of the pixel modification unit is derived from the masked bits from the destination operand and the unmasked bits which were operated on by the logic function unit. The byte mirror unit horizontally reflects a figure in the bit map via reversing the bit order of data bytes retrieved from the bit map. The present invention includes a high performance orthogonal rotator for a graphics processor that orthogonally rotates pixel regions in a bit map by an angle of 90 DEG or 270 DEG . Optionally, the pixel regions can be vertically mirrored as well as orthogonally rotated.

Inventors

  • 👤 Derek J. Lentz
  • 👤 Linley M. Young

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 13:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/30141; G06F9/30003; G06F9/3004; G06F9/30043; G06F9/30105; G06F9/30109; G06T; G06T1/00; G06T1/20

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 205 words
A system for bitwise manipulation of raster graphics data as a functional unit that executes instructions within a superscalar microprocessor and shares a memory interface with other of a plurality of functional units, comprising: bus means within the superscalar microprocessor, coupled to a logic function means, for receiving a source operand and a destination operand, said source and destination operands each comprising a plurality of bits; logic function means within the superscalar microprocessor for performing a bitwise logic operation between said source operand and said destination operand to generate a modified destination operand, said source operand being selected from the group comprising fixed data and a secondary bit map, said destination operand being a primary bit map corresponding to an image to be manipulated; a masking means within the superscalar microprocessor for generating multiplexer control signals; and a multiplexer within the superscalar microprocessor that performs, in response to said multiplexer control signals, bit-wise selection between said bits of said modified destination operand and said destination operand to provide an output, said multiplexer coupled to at least said logic function means so as to receive said modified destination operand, to said masking means to receive said set of multiplexer control signals, and to said destination operand.
Claim 2
Independent Claim 205 words
A system for bitwise manipulation of raster graphics data as a functional unit that executes instructions within a superscalar microprocessor and shares a memory interface with other of a plurality of functional units, comprising: bus means within the superscalar microprocessor, coupled to a logic function means, for receiving a source operand and a destination operand, said source and destination operands each comprising a plurality of bits; logic function means within the superscalar microprocessor for performing a bitwise logic operation between said source operand and said destination operand to generate a modified destination operand, said source operand being selected from the group comprising fixed data and a secondary bit map, said destination operand being a primary bit map corresponding to an image to be manipulated; a masking means within the superscalar microprocessor for generating multiplexer control signals; and a multiplexer within the superscalar microprocessor that performs, in response to said multiplexer control signals, bit-wise selection between said bits of said modified destination operand and said destination operand to provide an output, said multiplexer coupled to at least said logic function means so as to receive said modified destination operand, to said masking means to receive said set of multiplexer control signals, and to said destination operand.
Claim 3
Dependent Claim 65 words
The system of claim 1, wherein said masking means comprises a right mask generator, a left mask generator, and a combiner, said right and left mask generators for providing a respective right and left mask output for defining a respective right and left mask, said combiner for logically combining said right and left mask outputs with a mask operand to produce said multiplexer control signals.
Claim 4
Dependent Claim 47 words
The system of claim 1, further comprising a byte mirror means for moving bit map data forming a figure in said image, said bit map data organized as bytes and said bytes having a predetermined bit order, so that said figure is horizontally reflected in said image.
Claim 5
Dependent Claim 13 words
The system of claim 2, wherein said combiner performs a logic OR function.
Claim 6
Dependent Claim 29 words
The system of claim 3, further comprising a means for reversing said order of bits within each byte of an inputted mirror operand so as to effectuate said reflection.

References Cited (Backward Citations)

US4689738A Cited
US4648045A Cited
WO1986005299A1 Cited
US4874164A Cited
US5056041A Cited
US4941190A Cited
EP0354024A2 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-07-02 2000-01-01 2000-07-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-07-02 2004-01-01 2004-07-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-07-02 2008-01-01 2008-07-02 $7700.00 Window Closed / Lapsed

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