Patent US5530286A successfully refreshed from Google Patents.
US5530286A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Renesas Electronics Corp
•
Filing: 1994-08-22
•
Granted: 1996-06-25
•
Expires: 2014-08-22
Abstract
Abstract As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
Inventors
- 👤 Gen Murakami
- 👤 Kunihiro Tsubosaki
- 👤 Masahiro Ichitani
- 👤 Kunihiko Nishi
- 👤 Ichiro Anjoh
- 👤 Asao Nishimura
- 👤 Makoto Kitano
- 👤 Akihiro Yaguchi
- 👤 Sueo Kawai
- 👤 Masatsugu Ogata
- 👤 Syuuji Eguchi
- 👤 Hiroyoshi Kokaku
- 👤 Masanori Segawa
- 👤 Hiroshi Hozoji
- 👤 Takashi Yokoyama
- 👤 Noriyuki Kinjo
- 👤 Aizo Kaneda
- 👤 Junichi Saeki
- 👤 Shozo Nakamura
- 👤 Akio Hasebe
- 👤 Hiroshi Kikuchi
- 👤 Isamu Yoshida
- 👤 Takashi Yamazaki
- 👤 Kazuyoshi Oshima
- 👤 Tetsurou Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:25
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/117; H10W; H10W74/00; H10W74/10; H10W74/111; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W70/424; H10W70/427; H10W70/429; H10W70/435; H10W70/456; H10W70/458; H10W70/461; H10W72/00; H10W72/30; H10W72/90; H10W90/00; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/144; H05K1/18; H05K1/181; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3421; H10W70/60; H10W72/01; H10W72/015; H10W72/01515; H10W72/071; H10W72/072; H10W72/07251; H10W72/075; H10W72/07531; H10W72/07532; H10W72/07533; H10W72/20; H10W72/29; H10W72/321; H10W72/325; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/381; H10W72/50; H10W72/521; H10W72/522; H10W72/531; H10W72/536; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/5525; H10W72/553; H10W72/555; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/931; H10W72/932; H10W72/934; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W72/981; H10W72/983; H10W90/20; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
132 words
A semiconductor device comprising: a rectangular semiconductor chip having a principal surface with circuit elements and a plurality of external terminals; a plurality of leads extending over said principal surface, each comprising an inner lead portion and an outer lead portion, said inner lead portion including a first region, a second region and a stepped portion between said first region and said second region; a plurality of wires for electrically connecting said external terminals with each of said first regions of said inner lead portions; and a sealing member for sealing said semiconductor chip, said inner lead portions and said wires, said sealing member comprising a molding resin, wherein a distance between said second region and said principal surface is larger than a distance between said first region and said principal surface.
Claim 2
Dependent Claim
132 words
A semiconductor device comprising: a rectangular semiconductor chip having a principal surface with circuit elements and a plurality of external terminals; a plurality of leads extending over said principal surface, each comprising an inner lead portion and an outer lead portion, said inner lead portion including a first region, a second region and a stepped portion between said first region and said second region; a plurality of wires for electrically connecting said external terminals with each of said first regions of said inner lead portions; and a sealing member for sealing said semiconductor chip, said inner lead portions and said wires, said sealing member comprising a molding resin, wherein a distance between said second region and said principal surface is larger than a distance between said first region and said principal surface.
Claim 3
Dependent Claim
38 words
A semiconductor device according to claim 1, wherein said plurality of external terminals are arranged substantially at a central area of said rectangular semiconductor chip and substantially in parallel with the longer sides of said rectangular semiconductor chip.
Claim 4
Dependent Claim
82 words
A semiconductor device according to claim 2, further comprising: another plurality of external terminals arranged substantially in the central area of said rectangular semiconductor chip; a common lead comprising a first portion and a second portion, said first portion extending across said longer sides of said rectangular semiconductor chip and said second portion extending along said external terminals, said common lead comprising a lead to which terminals of said another plurality of external terminals are commonly connected by another plurality of wires.
Claim 5
Dependent Claim
24 words
A semiconductor device according to claim 1, wherein each of said inner lead portions extends across the longer sides of said rectangular semiconductor chip.
Claim 6
Dependent Claim
30 words
A semiconductor device according to claim 1, further comprising: an alpha ray shielding polyimide film formed all over said principal surface of said semiconductor chip except at said external terminals.
Claim 7
Dependent Claim
17 words
A semiconductor device according to claim 3, wherein a fixed potential is applied to said common lead.
References Cited (Backward Citations)
US5357139A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |