Synchronization detecting circuit

Abstract

Abstract A testing device is provided to test performance of transmission systems such as communication devices and transmission lines by transmitting and receiving specific patterns called pseudo-random patterns (i.e., PN patterns). A receiver unit of the testing device provides a synchronization detecting circuit. The synchronization detecting circuit comprises a pseudo-random-pattern creating circuit, a first coincidence detecting block, a second coincidence detecting block and an OR circuit. The first coincidence detecting block detects coincidence between a receiving-data input, a first detected-pattern input and a pseudo-random pattern created by the pseudo-random-pattern creating circuit so as to produce a first coincidence detecting signal. The second coincidence detecting block detects coincidence between the receiving-data input, a second detected-pattern input and the pseudo-random pattern so as to produce a second coincidence detecting signal. The first and second coincidence detecting signals are applied to the OR circuit, by which a synchronous detection signal is produced. Thus, synchronization between the receiving-data input and pseudo-random pattern is detected by the synchronous detection signal. Incidentally, each of the first and second detected-pattern inputs receives the pseudo-random pattern transmitted thereto through the transmission system; and the second detected-pattern input is delayed behind the first detected-pattern input by `m` bits (where `m` is an integer which is determined in advance).

Inventors

• 👤 Keiji Negi

Bibliographic Details