Firing pattern output generation for AC traction inverter control

Claim 1

A control circuit for generating gating signals for each of a plurality of semiconductor switching devices in an electric power conversion circuit, comprising: a microcomputer operable to compute timing delta for application of gating signals so as to generate a desired power output of the conversion circuit; a volatile memory having a plurality of addressable memory locations, said memory locations having sequential addresses; a timer-counter adapted for outputting digitized time signals at each of a plurality of time increments, each of the time signals comprising an address for a respective one of the memory locations in said memory whereby each of the memory locations is sequentially addressed by a corresponding one of the time signals as said timer-counter outputs sequential time signals; said microcomputer transferring said gating signals to memory locations in said memory corresponding to said computed timing data whereby said gating signals are output from said memory in response to said corresponding memory locations being addressed by said time signal; and output means coupled to said memory and responsive to said gating signals for supplying gating signals to the semiconductor switching devices.

Claim 9

A method of generating gating signals for each of a plurality of electric switching devices in an electric power conversion circuit comprising the steps of: computing timing data representative of a relative time for application of gating signals to each of the switching devices for generating a desired electric power output from the conversion circuit; providing a volatile memory having a plurality of addressable memory locations wherein each memory location address corresponds to a selected time increment; generating a sequence of timing signals having a memory address format such that each of the timing signals addresses a unique memory location in the volatile memory; and storing gating signals for the electric switching devices in memory locations in the volatile memory corresponding to the computed timing data whereby the gating signals are accessed in the memory at the computed relative time by the sequential addressing of the memory locations by the timing signals.

Claim 10

A method of generating gating signals for each of a plurality of electric switching devices in an electric power conversion circuit comprising the steps of: computing timing data representative of a relative time for application of gating signals to each of the switching devices for generating a desired electric power output from the conversion circuit; providing a volatile memory having a plurality of addressable memory locations wherein each memory location address corresponds to a selected time increment; generating a sequence of timing signals having a memory address format such that each of the timing signals addresses a unique memory location in the volatile memory; and storing gating signals for the electric switching devices in memory locations in the volatile memory corresponding to the computed timing data whereby the gating signals are accessed in the memory at the computed relative time by the sequential addressing of the memory locations by the timing signals.

Claim 12

A method of generating gating signals for each of a plurality of electric switching devices in an electric power conversion circuit comprising the steps of: computing timing data representative of a relative time for application of gating signals to each of the switching devices for generating a desired electric power output from the conversion circuit; providing a volatile memory having a plurality of addressable memory locations and operatively associating a first group of the memory locations with a second group of the memory locations on a one-to-one basis; generating a sequence of timing signals having a memory address format such that each of the timing signals addresses a unique memory location in the volatile memory; storing timing data for application of the gating signals to the electric switching devices in sequentially addressable memory locations in the first group of memory locations in the volatile memory and storing gating signals corresponding to the timing data in the second group of memory locations; comparing the timing data stored in a first memory location in the first group of memory locations to the timing signals until one of the timing signals matches the stored timing data and thereupon generating a match signal to effect a transfer of the corresponding gating signals to the power conversion circuit; and repeating the step of comparing for each memory location of the first group until a last location is accessed and thereupon returning to the first memory location and continuing.

Claim 13

A method of generating gating signals for each of a plurality of electric switching devices in an electric power conversion circuit comprising the steps of: computing timing data representative of a relative time for application of gating signals to each of the switching devices for generating a desired electric power output from the conversion circuit; providing a volatile memory having a plurality of addressable memory locations and operatively associating a first group of the memory locations with a second group of the memory locations on a one-to-one basis; generating a sequence of timing signals having a memory address format such that each of the timing signals addresses a unique memory location in the volatile memory; storing timing data for application of the gating signals to the electric switching devices in sequentially addressable memory locations in the first group of memory locations in the volatile memory and storing gating signals corresponding to the timing data in the second group of memory locations; comparing the timing data stored in a first memory location in the first group of memory locations to the timing signals until one of the timing signals matches the stored timing data and thereupon generating a match signal to effect a transfer of the corresponding gating signals to the power conversion circuit; and repeating the step of comparing for each memory location of the first group until a last location is accessed and thereupon returning to the first memory location and continuing.