US5168439A
Expired / Lapsed
US
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Inverter control method and apparatus
Assignee: General Electric Co
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Filing: 1990-11-27
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Granted: 1992-12-01
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Expires: 2010-11-27
Abstract
Abstract A method and apparatus for controlling an inverter circuit to convert dc voltage to variable amplitude and frequency ac voltage use firing pattern tables which are stored and selected in accordance with a required voltage level for the ac voltage. The firing pattern tables are accessed by writable timers which both address the firing pattern tables and define the times between readout of consecutive entires of the firing pattern tables. If requirements of the ac voltage being produced are changed, a new firing pattern table is selected at the end of the currently selected pattern table. Further, as the required frequency of the ac voltage being produced changes during the readout of a selected firing pattern table, the times written into the writable timers are changed accordingly to vary the frequency of the ac signal on the fly. Angle tables corresponding to the pattern tables are stored and accessed by a control processor to determine the times written into the timers. The angle tables are stored in terms of angles between transitions of the pattern tables and one or more angle tables are provided for each pattern table. The amplitude of the ac voltage being produced is determined by pattern table selection and angle table section, if more than one angle table is provided for a given pattern table, and the frequency of the ac voltage being produced is determined by the time signals generated by the processor.
Inventors
- 👤 Ajith Kumar
- 👤 Thomas D. Stitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:53
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02M7/53873
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
166 words
A control circuit for generating drive signals for an inverter circuit for converting dc voltage to three phase variable amplitude and frequency ac voltage comprising: memory means for storing firing pattern signals defining on/off status of switching devices making up the inverter circuit; writable timing circuit means for addressing the memory means to read the firing pattern signals from the memory means; processor means for writing times into the writable timing circuit means for controlling the voltage level and frequency of the three phase ac voltage generated by the inverter, wherein the frequency of a signal between the writable timing circuit means and an address counter means is substantially continuously variable under the control of the processor means; and interrupt controller means, operatively connected to the writable timing circuit means and the processor means, for generating interrupt of the processor means upon time outs of the writable timing circuit means such that the processor means maintains at least one of the timing circuit means written ahead.
Claim 2
Dependent Claim
166 words
A control circuit for generating drive signals for an inverter circuit for converting dc voltage to three phase variable amplitude and frequency ac voltage comprising: memory means for storing firing pattern signals defining on/off status of switching devices making up the inverter circuit; writable timing circuit means for addressing the memory means to read the firing pattern signals from the memory means; processor means for writing times into the writable timing circuit means for controlling the voltage level and frequency of the three phase ac voltage generated by the inverter, wherein the frequency of a signal between the writable timing circuit means and an address counter means is substantially continuously variable under the control of the processor means; and interrupt controller means, operatively connected to the writable timing circuit means and the processor means, for generating interrupt of the processor means upon time outs of the writable timing circuit means such that the processor means maintains at least one of the timing circuit means written ahead.
Claim 3
Dependent Claim
29 words
The control circuit of claim 1 wherein the firing pattern signals are stored in firing pattern tables and the processor means further provides for selecting among the pattern tables.
Claim 4
Dependent Claim
73 words
The control circuit of claim 2 wherein the processor means further comprises angle table storage means for storing angle tables defining transition times for sequencing between consecutively read ones of the firing pattern signals within corresponding firing signal pattern tables, the transition times being stored in terms of pulse width angles of the transition times and the processor means using the angle tables to determine times written into the writable timing circuit means.
Claim 5
Dependent Claim
20 words
The control circuit of claim 3 wherein the angle tables include at least one angle table for each pattern table.
Claim 6
Dependent Claim
215 words
A control circuit for generating drive signals for an inverter circuit which converts dc voltage to three phase variable amplitude and frequency ac voltage comprising: first memory means for storing firing pattern tables including inverter control signals defining on/off status of switching devices making up the inverter circuit: writable timing circuit means for addressing the first memory means to read the firing pattern tables stored within the first memory means in accordance with times written into the writable timing circuit means; processor means for selecting pattern tables within the first memory means in response to a desired voltage level for the three phase ac voltage generated by the inverter and for writing times into the writable timing circuit means in response to a desired frequency for a three phase ac voltage generated by the inverter wherein the frequency of a signal between the writable timing circuit means and an address counter means is substantially continuously variable under the control of the processor means; and interrupt controller means, operatively connected to the writable timing circuit means and the processor means, for generating interrupts of the processor means upon time outs of the writable timer means such that the processor means maintains up to six milliseconds of the times written ahead into the writable timing circuit means.
Claim 7
Dependent Claim
215 words
A control circuit for generating drive signals for an inverter circuit which converts dc voltage to three phase variable amplitude and frequency ac voltage comprising: first memory means for storing firing pattern tables including inverter control signals defining on/off status of switching devices making up the inverter circuit: writable timing circuit means for addressing the first memory means to read the firing pattern tables stored within the first memory means in accordance with times written into the writable timing circuit means; processor means for selecting pattern tables within the first memory means in response to a desired voltage level for the three phase ac voltage generated by the inverter and for writing times into the writable timing circuit means in response to a desired frequency for a three phase ac voltage generated by the inverter wherein the frequency of a signal between the writable timing circuit means and an address counter means is substantially continuously variable under the control of the processor means; and interrupt controller means, operatively connected to the writable timing circuit means and the processor means, for generating interrupts of the processor means upon time outs of the writable timer means such that the processor means maintains up to six milliseconds of the times written ahead into the writable timing circuit means.
Claim 8
Dependent Claim
53 words
The control circuit of claim 5 wherein the processor means comprises second memory means for storing angle tables defining transition times of the inverter control signals in terms of pulse width angles for the transition times, the processor means using the angle tables for determining times written into the writable timing circuit means.
Claim 9
Dependent Claim
20 words
The control circuit of claim 6 wherein the angle tables include at least one angle table for each pattern table.
Claim 10
Dependent Claim
34 words
The control circuit of claim 7 wherein processor means further provides for selecting among the angle tables to further define the voltage level of the three phase ac voltage generated by the inverter circuit.
Claim 11
Independent Claim
130 words
A method for generating drive signals for an inverter circuit for converting dc voltage to three phase variable amplitude and frequency ac voltage comprising the steps of: storing firing pattern signals defining on/off status of switching devices making up the inverter circuit; reading the firing pattern signals in accordance with writable read times to access the firing pattern signals for control of the inverter circuit; writing the read times to control the voltage level and frequency of the three phase ac voltage generated by the inverter into a writable timing circuit means wherein the frequency of a signal between the writable timing circuit means and address counter means is substantially continuous variable under the control of a processor means; and generating interrupts upon time outs of the writable circuit means.
Claim 12
Independent Claim
130 words
A method for generating drive signals for an inverter circuit for converting dc voltage to three phase variable amplitude and frequency ac voltage comprising the steps of: storing firing pattern signals defining on/off status of switching devices making up the inverter circuit; reading the firing pattern signals in accordance with writable read times to access the firing pattern signals for control of the inverter circuit; writing the read times to control the voltage level and frequency of the three phase ac voltage generated by the inverter into a writable timing circuit means wherein the frequency of a signal between the writable timing circuit means and address counter means is substantially continuous variable under the control of a processor means; and generating interrupts upon time outs of the writable circuit means.
Claim 13
Dependent Claim
59 words
The method of claim 9 wherein the step of storing firing pattern signals comprises storing tables of firing pattern signals corresponding to voltage levels of the three phase ac voltage generated by the inverter circuit and the method further comprises selecting among the tables as a function of the three phase ac voltage to be generated by the inverter.
Claim 14
Dependent Claim
65 words
The method of claim 10 further comprising the step of storing angle tables defining transition times for sequencing between consecutively read ones of the firing pattern signals within corresponding firing signal pattern tables, the transition times being stored in terms of pulse width angles of the transition times, the method further comprising the step of determining the read times in accordance with the angle tables.
Claim 15
Dependent Claim
18 words
The method of claim 11 wherein said angle tables include at least one angle for each pattern table.
Claim 16
Dependent Claim
25 words
The method of claim 12 further comprising the step of selecting an angle table to define the voltage level of the three phase ac voltage.
Claim 17
Dependent Claim
165 words
An inverter control circuit comprising: a triangle interception PWM controller means operatively connected to the inverter; first memory means for storing firing pattern signals defining on/off status of switching devices contained in an inverter circuit; writable timing circuit means for addressing the first memory means for reading the firing pattern signals from the first memory means; processor means for writing times into the writable timing circuit means and for controlling the voltage level and frequencies of a three phase AC voltage generated by the inverter wherein the frequency of a signal between the writable circuits and an address counter mean is substantially continuously variable under the control of the processor means; and interrupt controller means, interconnected between the writable timing circuit means and the processor mean, for generating interrupts of the processor means upon time outs of the writable timing circuit means, the interrupt controller means allows the processor means to maintain a defined portion of the times written ahead into the writable timing means.
Claim 18
Dependent Claim
165 words
An inverter control circuit comprising: a triangle interception PWM controller means operatively connected to the inverter; first memory means for storing firing pattern signals defining on/off status of switching devices contained in an inverter circuit; writable timing circuit means for addressing the first memory means for reading the firing pattern signals from the first memory means; processor means for writing times into the writable timing circuit means and for controlling the voltage level and frequencies of a three phase AC voltage generated by the inverter wherein the frequency of a signal between the writable circuits and an address counter mean is substantially continuously variable under the control of the processor means; and interrupt controller means, interconnected between the writable timing circuit means and the processor mean, for generating interrupts of the processor means upon time outs of the writable timing circuit means, the interrupt controller means allows the processor means to maintain a defined portion of the times written ahead into the writable timing means.
Claim 19
Dependent Claim
30 words
The inverter control circuit of claim 14 wherein the firing pattern signals are stored in firing pattern tables and the processor means further provides for selecting among the pattern tables.
Claim 20
Dependent Claim
74 words
The inverter control circuit of claim 14 wherein the processor means further comprises: angle table storage means for storing angle tables defining transition times for sequencing between consecutively read outs of the firing pattern signals within corresponding firing signal pattern tables, the transition times being stored in terms of pulse width angles of the transition times and the processor means using the angle tables to determine times written into the writable timing circuit means.
Claim 21
Dependent Claim
16 words
The inverter control circuit of claim 14 wherein the defined portion is up to six milliseconds.
Claim 22
Dependent Claim
22 words
The method of claim 9 further comprising the step of: maintaining at least one of the writable timing circuit means written ahead.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-01 | 1996-06-01 | 1996-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-01 | 2000-06-01 | 2000-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-01 | 2004-06-01 | 2004-12-01 | $7700.00 | Window Closed / Lapsed |