Patent US5528306A successfully refreshed from Google Patents.
US5528306A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video signal processing circuit for converting digital color difference signals into a carrier chrominance signal
Assignee: Victor Company of Japan Ltd
•
Filing: 1995-05-30
•
Granted: 1996-06-18
•
Expires: 2015-05-30
Abstract
Abstract A video signal processing circuit capable of converting digital color difference signals directly into a carrier chrominance signal is described. The processing circuit includes a first flip-flop for latching the first sampling clock signal of the first and second color difference signals with a second sampling clock signal having a frequency which is an integer multiple of a subcarrier frequency of the carrier chrominance signal to be produced, second and third flip-flops for respectively latching the first and second color difference signals with a third sampling clock signal obtained from the first flip-flop, and carrier chrominance signal generating circuit for generating the carrier chrominance signal from the first and second color difference signals outputted from the second and third flip-flops.
Inventors
- 👤 Tamotsu Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:36
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0117; H04N7/0122; H04N11/00; H04N11/06; H04N11/20
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
135 words
A video signal processing circuit for processing first and second color difference signals, both of which are sampled at a single sampling rate of first sampling clock signal, and for producing a carrier chrominance signal, said processing circuit comprising: a first flip-flop for latching said first sampling clock signal of said first and second color difference signals with a second sampling clock signal having a frequency which is an integer multiple of a subcarrier frequency of said carrier chrominance signal to be produced; second and third flip-flops for respectively latching said first and second color difference signals with a third sampling clock signal obtained from said first flip-flop; and carrier chrominance signal generating means for generating said carrier chrominance signal from said first and second color difference signals outputted from said second and third flip-flops.
Claim 2
Dependent Claim
135 words
A video signal processing circuit for processing first and second color difference signals, both of which are sampled at a single sampling rate of first sampling clock signal, and for producing a carrier chrominance signal, said processing circuit comprising: a first flip-flop for latching said first sampling clock signal of said first and second color difference signals with a second sampling clock signal having a frequency which is an integer multiple of a subcarrier frequency of said carrier chrominance signal to be produced; second and third flip-flops for respectively latching said first and second color difference signals with a third sampling clock signal obtained from said first flip-flop; and carrier chrominance signal generating means for generating said carrier chrominance signal from said first and second color difference signals outputted from said second and third flip-flops.
Claim 3
Dependent Claim
55 words
The video signal processing circuit claimed in claim 1, wherein said carrier chrominance signal generating means comprises a selector for selectively switching and outputting said first and second color difference signals respectively outputted from said second and third flip-flops and an inverter for inverting a polarity of an output of said selector every predetermined period.
Claim 4
Dependent Claim
16 words
The video signal processing circuit claimed in claim 2, wherein said inverter is an EXOR circuit.
Claim 5
Dependent Claim
24 words
The video signal processing circuit claimed in claim 1, wherein said third sampling clock signal is a polarity inverted output from said first flip-flop.
Claim 6
Dependent Claim
24 words
The video signal processing circuit claimed in claim 2, wherein said third sampling clock signal is a polarity inverted output from said first flip-flop.
Claim 7
Dependent Claim
24 words
The video signal processing circuit claimed in claim 3, wherein said third sampling clock signal is a polarity inverted output from said first flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-18 | 1999-12-18 | 2000-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-18 | 2003-12-18 | 2004-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-18 | 2007-12-18 | 2008-06-18 | $7700.00 | Window Closed / Lapsed |