Scheme camera employing compression recording

Claim 1

A CCD digital camera, comprising: a data processing unit; a matrix of photoelectric detectors, each photoelectric detector of said matrix of photoelectric detectors outputting an electrical signal of a first size corresponding to light received from an image of an object to be photographed; a plurality of vertical transfer shift registers extending in a column direction that are connected to a corresponding photoelectric detector of said matrix of photoelectric detectors, each of said plurality of vertical transfer shift registers storing a charge corresponding to said electrical signal output by each photoelectric detector of said matrix of photoelectric detectors; a horizontal transfer shift register extending in a row direction that is connected to an output of a corresponding one of said plurality of vertical transfer shift registers; a memory sized to store a predetermined portion of said electrical signal predetermined portion said electrical signal being equal to a second size that is smaller than said first size of said electrical signal; a controller that controls a transfer of said predetermined portion of said electrical signal to said memory; a data compression unit that compresses said predetermined portion of said electrical signal stored in said memory and outputs a compressed signal corresponding to said predetermined portion of said electrical signal; and a storage device that stores said compressed electrical signal, wherein said data processing unit outputs said electrical signal to said memory, said controller controlling said plurality of vertical transfer shift registers to shift said charge to said horizontal transfer shift register and to control horizontal transfer shift register to transfer said charge to said data processing unit, said controller outputting vertical drive pulses for shifting said charge stored in said vertical transfer shift registers down to an adjacent register and to inhibit a transfer of a subsequent predetermined portion of said electrical signal to said memory until all of said predetermined portion of said electrical signal has been compressed by said data compression unit and stored in said storage device, said controller inhibiting an output of said vertical drive pulses until all of said predetermined portion of said electrical signal has been stored in said storage device.