US5525971A
Expired / Lapsed
US
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Integrated circuit
Assignee: ARM Ltd
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Filing: 1994-08-25
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Granted: 1996-06-11
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Expires: 2014-08-25
Abstract
Abstract An integrated circuit comprises a plurality of data handling devices interconnected to exchange data by an interconnection bus during a first mode of operation; and diagnostic control means, responsive to a diagnostic device external to the integrated circuit, for controlling one or more of the data handling devices to exchange diagnostic data with the diagnostic device via the interconnection bus during a second, diagnostic, mode of operation.
Inventors
- 👤 David W. Flynn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 04:51
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F11/26; G06F11/273; G06F11/2733
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
97 words
An integrated circuit comprising: a plurality of data handling devices interconnected to exchange data by an interconnection bus during a first mode of operation, said data handling devices comprising one or more bus master data handling devices and one or more bus slave data handling devices; and diagnostic control means, responsive to a diagnostic device external to said integrated circuit, comprising a diagnostic bus master data handling device for controlling one or more of said data handling devices to exchange diagnostic data with said diagnostic device via said interconnection bus during a second, diagnostic, mode of operation.
Claim 2
Dependent Claim
97 words
An integrated circuit comprising: a plurality of data handling devices interconnected to exchange data by an interconnection bus during a first mode of operation, said data handling devices comprising one or more bus master data handling devices and one or more bus slave data handling devices; and diagnostic control means, responsive to a diagnostic device external to said integrated circuit, comprising a diagnostic bus master data handling device for controlling one or more of said data handling devices to exchange diagnostic data with said diagnostic device via said interconnection bus during a second, diagnostic, mode of operation.
Claim 3
Dependent Claim
60 words
An integrated circuit according to claim 1, comprising: arbitration means, responsive to a request for control of said interconnection bus by one or more of said bus master data handling devices, for allocating control of said interconnection bus to a bus master data handling device in dependence on a predetermined priority order associated with said bus master data handling devices.
Claim 4
Dependent Claim
35 words
An integrated circuit according to claim 2, in which said diagnostic control means has a higher priority, in said predetermined priority order, than all other bus master data handling devices connected to said interconnection bus.
Claim 5
Dependent Claim
34 words
An integrated circuit according to claim 1, in which said diagnostic control means comprises means for selectively controlling all other data handling devices connected to said interconnection bus to operate as bus slave devices.
Claim 6
Dependent Claim
33 words
An integrated circuit according to claim 1, in which said diagnostic data comprises one or more successive diagnostic vectors according to a predetermined diagnostic procedure associated with a data handling device under test.
Claim 7
Dependent Claim
28 words
An integrated circuit according to claim 5, in which the one or more diagnostic vectors comprise an address vector for selecting a data handling device to be tested.
Claim 8
Dependent Claim
24 words
An integrated circuit according to claim 1, in which said integrated circuit is operable under the control of successive cycles of a clocking signal.
Claim 9
Dependent Claim
61 words
An integrated circuit according to claim 7, in which said diagnostic control means is responsive to a control signal received from the diagnostic device during a current cycle of the clocking signal, to control one or more of said data handling devices to exchange diagnostic data with said diagnostic device via said interconnection bus during subsequent cycles of said clocking signal.
Claim 10
Dependent Claim
56 words
An integrated circuit according to claim 1, comprising a data buffer, said data buffer providing an external data bus enabling transfer of data between said interconnection bus and data handling devices external to said integrated circuit; and in which said diagnostic control means is operable to place said external data bus into a high impedance state.
Claim 11
Independent Claim
98 words
A method of operation of an integrated circuit having a plurality of data handling devices interconnected to exchange data by an interconnection bus during a first mode of operation, said data handling devices comprising one or more bus master data handling devices and one or more bus slave data handling device said method comprising the step of: controlling one or more of said data handling devices with a diagnostic bus master data handling device to exchange diagnostic data with a diagnostic device external to said integrated circuit via said interconnection bus during a second, diagnostic, mode of operation.
Claim 12
Independent Claim
98 words
A method of operation of an integrated circuit having a plurality of data handling devices interconnected to exchange data by an interconnection bus during a first mode of operation, said data handling devices comprising one or more bus master data handling devices and one or more bus slave data handling device said method comprising the step of: controlling one or more of said data handling devices with a diagnostic bus master data handling device to exchange diagnostic data with a diagnostic device external to said integrated circuit via said interconnection bus during a second, diagnostic, mode of operation.
References Cited (Backward Citations)
US4406007A
Cited
EP0023413A1
Cited
US4403287A
Cited
EP0243113A2
Cited
US4910735A
Cited
US4947395A
Cited
US5245531A
Cited
US5416919A
Cited
US5115435A
Cited
US5260946A
Cited
US5442643A
Cited
US5373504A
Cited
US5387229A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-11 | 1999-12-11 | 2000-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-11 | 2003-12-11 | 2004-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-11 | 2007-12-11 | 2008-06-11 | $7700.00 | Window Closed / Lapsed |