§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0243113A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data processor

Assignee: Hitachi Ltd
•
Filing: 1987-04-16
•
Granted: —
•
Expires: 2007-04-16
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A single chip microcomputer has functional blocks such as a central processing unit (CPU), a ROM for storing programs, a RAM for storing data and an I/O circuit for the input and output of the data. These functional blocks are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus (IB) to which the address data must be supplied by the CPU. A buffer circuit (BUF) is adapted to be supplied with address data from external devices is connected to the internal bus (IB). When the functional blocks are tested, address data is supplied directly to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from that area of the predetermined functional block, passing through the buffer circuit (BUF) and is read out directly to the external devices. Hence, the testing efficiency is improved.

Inventors

  • 👤 Yasushi Akao
  • 👤 Haruo Keida
  • 👤 Shinkichi Hotta

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 08:10
CPC Classifications
G; G06; G06F; G06F15/00; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 75 words
A data processor, comprising a central processing unit (CPU) and a plurality of functional blocks (TM, RAM, ROM) coupled to the central processing unit (CPU) by way of an internal bus (IB), characterised in that: a buffer circuit (BUF) is connected to the internal bus (IB) which is to be supplied with address data from the central processing unit (CPU), the buffer circuit (BUF) being adapted to be supplied with address data from external devices.
Claim 2
Dependent Claim 75 words
A data processor, comprising a central processing unit (CPU) and a plurality of functional blocks (TM, RAM, ROM) coupled to the central processing unit (CPU) by way of an internal bus (IB), characterised in that: a buffer circuit (BUF) is connected to the internal bus (IB) which is to be supplied with address data from the central processing unit (CPU), the buffer circuit (BUF) being adapted to be supplied with address data from external devices.
Claim 3
Dependent Claim 45 words
A data processor according to claim 1, wherein the buffer circuit (BUF) is adapted to be supplied with signals for controlling the operations of the functional blocks (TM, RAM, ROM) when the buffer circuit (BUF) is supplied with the address data from the external devices.
Claim 4
Dependent Claim 49 words
A data processor according to claim 1 or claim 2, wherein data of an area is selected based on the address data supplied from the external devices and the buffer circuit (BUF) is capable of outputting the data to the external devices by way of the internal bus (IB).

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag