Patent US5523972A successfully refreshed from Google Patents.
US5523972A
Expired / Lapsed
US
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Method and apparatus for verifying the programming of multi-level flash EEPROM memory
Assignee: Intel Corp
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Filing: 1994-06-02
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Granted: 1996-06-04
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Expires: 2014-06-02
Abstract
Abstract A programming verify circuit for controlling the memory cells to which programming voltages are applied, the circuit including a comparator for testing the state of each cell being programmed with the state to which the cell is being programmed, and a program load circuit which responds to the result of the test by the comparator to hold a condition for each memory cell being programmed to indicate whether the memory cell should be further programmed, each program load circuit including circuitry for precluding the holding of a condition indicating further programming is necessary once the associated memory cell has been initially verified as programmed by the comparator.
Inventors
- 👤 Mamun Rashid
- 👤 Mark Bauer
- 👤 Chakravarthy Yarlagadda
- 👤 Phillip M. L. Kwong
- 👤 Albert Fazio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:08
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/52; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
129 words
A programming verify circuit for controlling the application of programming voltages to a plurality of memory cells in a flash EEPROM memory array, each of the memory cells capable of storing a plurality of states, the circuit comprising: a comparator for testing a current state of each memory cell being programmed with a state to which the memory cell is to be programmed, and a program load circuit coupled to the comparator, storing for each memory cell a value output from the comparator indicating whether the memory cell should be further programmed, the program load circuit including circuitry for precluding storing for each memory cell a value indicating further programming of the memory cell is necessary once the memory cell has been initially verified by the comparator as programmed.
Claim 2
Dependent Claim
129 words
A programming verify circuit for controlling the application of programming voltages to a plurality of memory cells in a flash EEPROM memory array, each of the memory cells capable of storing a plurality of states, the circuit comprising: a comparator for testing a current state of each memory cell being programmed with a state to which the memory cell is to be programmed, and a program load circuit coupled to the comparator, storing for each memory cell a value output from the comparator indicating whether the memory cell should be further programmed, the program load circuit including circuitry for precluding storing for each memory cell a value indicating further programming of the memory cell is necessary once the memory cell has been initially verified by the comparator as programmed.
Claim 3
Dependent Claim
48 words
The programming verify circuit of claim 1 wherein the circuitry for precluding storing for each memory cell a value comprises a latch and a feedback circuit for controlling input to the latch depending on the state of the latch when the value output from the comparator is applied.
Claim 4
Dependent Claim
19 words
The programming verify circuit of claim 1 further comprising a flag circuit for prohibiting overprogramming of a memory cell.
Claim 5
Dependent Claim
33 words
The programming verify circuit of claim 3 wherein the flag circuit comprises a register for receiving input from the program load circuit indicating whether a memory cell is programmed or to be programmed.
Claim 6
Dependent Claim
22 words
The programming verify circuit of claim 3 further comprising a controller circuit for resetting the program load circuit and the flag circuit.
Claim 7
Dependent Claim
157 words
A computer system comprising: a computer bus, a central processor coupled to the computer bus, a flash EEPROM memory array coupled to the computer bus comprising: a plurality of memory cells arranged in rows and columns, each of the memory cells capable of assuming a plurality of states, a programming verify circuit for controlling the application of programming voltages to the memory cells, the circuit comprising: a comparator for testing a current state of each memory cell being programmed with a state to which the memory cell is to be programmed, and a program load circuit coupled to the comparator, storing for each memory cell a value output from the comparator indicating whether the memory cell should be further programmed, the program load circuit including circuitry for precluding storing for each memory cell a value indicating further programming of the memory cell is necessary once the memory cell has been initially verified by the comparator as programmed.
Claim 8
Dependent Claim
157 words
A computer system comprising: a computer bus, a central processor coupled to the computer bus, a flash EEPROM memory array coupled to the computer bus comprising: a plurality of memory cells arranged in rows and columns, each of the memory cells capable of assuming a plurality of states, a programming verify circuit for controlling the application of programming voltages to the memory cells, the circuit comprising: a comparator for testing a current state of each memory cell being programmed with a state to which the memory cell is to be programmed, and a program load circuit coupled to the comparator, storing for each memory cell a value output from the comparator indicating whether the memory cell should be further programmed, the program load circuit including circuitry for precluding storing for each memory cell a value indicating further programming of the memory cell is necessary once the memory cell has been initially verified by the comparator as programmed.
Claim 9
Dependent Claim
47 words
The computer system of claim 6 wherein the circuitry for precluding storing for each memory cell a value comprises a latch and a feedback circuit for controlling input to the latch depending on the state of the latch when the value output from the comparator is applied.
Claim 10
Dependent Claim
18 words
The computer system of claim 6 further comprising a flag circuit for prohibiting overprogramming of a memory cell.
Claim 11
Dependent Claim
32 words
The computer system of claim 8 wherein the flag circuit comprises a register for receiving input from the program load circuit indicating whether a memory cell is programmed or to be programmed.
Claim 12
Dependent Claim
21 words
The computer system of claim 8 further comprising a controller circuit for resetting the program load circuit and the flag circuit.
Claim 13
Dependent Claim
129 words
A programming verify circuit for controlling the application of programming voltages to a plurality of memory cells in a memory array, each of the memory cells capable of storing a plurality of data bits, the circuit comprising: comparator means for testing a current state of each memory cell being programmed with a state to which the memory cell is to be programmed, and storing means coupled to the comparator means for storing for each memory cell a value output from the comparator means indicating whether the memory cell should be further programmed, the storing means including means for precluding storing for each memory cell a value indicating further programming of the memory cell is necessary once the memory cell has been initially verified by the comparator means as programmed.
Claim 14
Dependent Claim
129 words
A programming verify circuit for controlling the application of programming voltages to a plurality of memory cells in a memory array, each of the memory cells capable of storing a plurality of data bits, the circuit comprising: comparator means for testing a current state of each memory cell being programmed with a state to which the memory cell is to be programmed, and storing means coupled to the comparator means for storing for each memory cell a value output from the comparator means indicating whether the memory cell should be further programmed, the storing means including means for precluding storing for each memory cell a value indicating further programming of the memory cell is necessary once the memory cell has been initially verified by the comparator means as programmed.
Claim 15
Dependent Claim
49 words
The programming verify circuit of claim 11 wherein the means for precluding storing for each memory cell a value comprises a latch and a feedback circuit for controlling input to the latch depending on the state of the latch when the value output from the comparator means is applied.
Claim 16
Dependent Claim
17 words
The programming verify circuit of claim 11 further comprising means for prohibiting overprogramming of a memory cell.
Claim 17
Dependent Claim
38 words
The programming verify circuit of claim 13 wherein the means for prohibiting overprogramming of a memory cell comprises a register for receiving input from the storing means indicating whether a memory cell is programmed or to be programmed.
Claim 18
Dependent Claim
27 words
The programming verify circuit of claim 13 further comprising a controller circuit for resetting the storing means and the means for prohibiting overprogramming of a memory cell.
Claim 19
Dependent Claim
140 words
A computer system comprising: computer bus means, central processing means coupled to the computer bus means, a memory array coupled to the computer bus means comprising: a plurality of memory cells arranged in rows and columns, each of the memory cells capable of storing a plurality of states, comparator means for testing a current state of each memory cell being programmed with a state to which the memory cell is to be programmed, and storing means coupled to the comparator means for storing for each memory cell a value output from the comparator means indicating whether the memory cell should be further programmed, the storing means including means for precluding storing for each memory cell a value indicating further programming of the memory cell is necessary once the memory cell has been initially verified by the comparator means as programmed.
Claim 20
Dependent Claim
140 words
A computer system comprising: computer bus means, central processing means coupled to the computer bus means, a memory array coupled to the computer bus means comprising: a plurality of memory cells arranged in rows and columns, each of the memory cells capable of storing a plurality of states, comparator means for testing a current state of each memory cell being programmed with a state to which the memory cell is to be programmed, and storing means coupled to the comparator means for storing for each memory cell a value output from the comparator means indicating whether the memory cell should be further programmed, the storing means including means for precluding storing for each memory cell a value indicating further programming of the memory cell is necessary once the memory cell has been initially verified by the comparator means as programmed.
Claim 21
Dependent Claim
48 words
The computer system of claim 16 wherein the means for precluding storing for each memory cell a value comprises a latch and a feedback circuit for controlling input to the latch depending on the state of the latch when the value output from the comparator means is applied.
Claim 22
Dependent Claim
16 words
The computer system of claim 16 further comprising means for prohibiting overprogramming of a memory cell.
Claim 23
Dependent Claim
37 words
The computer system of claim 18 wherein the means for prohibiting overprogramming of a memory cell comprises a register for receiving input from the storing means indicating whether a memory cell is programmed or to be programmed.
Claim 24
Dependent Claim
26 words
The computer system of claim 18 further comprising a controller circuit for resetting the storing means and the means for prohibiting overprogramming of a memory cell.
References Cited (Backward Citations)
US5293610A
Cited
US5287317A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |