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US5523971A
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Non-volatile memory cell for programmable logic device
Assignee: Xilinx Inc
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Filing: 1995-03-16
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Granted: 1996-06-04
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Expires: 2015-03-16
Abstract
Abstract The present invention provides a memory cell which includes a pair of flash EEPROM cells. One flash EEPROM cell is programmed and the other flash EEPROM cell is simultaneously erased by a single programming pulse. Because the configuration memory cell includes flash EEPROM cells, and therefore is non-volatile, a power down does not require reprogramming or refreshing of the configuration bit stored in the memory cell.
Inventors
- 👤 Kameswara K. Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 01:34
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
163 words
A memory cell comprising: a first non-volatile programmable and erasable storage cell; a second non-volatile programmable and erasable storage cell, wherein each storage cell includes a first terminal, a second terminal, and a control terminal, wherein the first terminals of said first and second storage cells are connected to a power bus, wherein the second terminal of said first storage cell is selectively connected to a first bitline and the second terminal of said second storage cell is selectively connected to a second bitline, wherein the control terminal of said first storage cell is connected to the second terminal of said second storage cell and a first output line, and wherein the control terminal of said second storage cell is connected to the second terminal of said first storage cell and a second output line; and means for forming a latch including said first and second storage cells, wherein said means for forming is operatively coupled to said first and second output lines.
Claim 2
Dependent Claim
163 words
A memory cell comprising: a first non-volatile programmable and erasable storage cell; a second non-volatile programmable and erasable storage cell, wherein each storage cell includes a first terminal, a second terminal, and a control terminal, wherein the first terminals of said first and second storage cells are connected to a power bus, wherein the second terminal of said first storage cell is selectively connected to a first bitline and the second terminal of said second storage cell is selectively connected to a second bitline, wherein the control terminal of said first storage cell is connected to the second terminal of said second storage cell and a first output line, and wherein the control terminal of said second storage cell is connected to the second terminal of said first storage cell and a second output line; and means for forming a latch including said first and second storage cells, wherein said means for forming is operatively coupled to said first and second output lines.
Claim 3
Dependent Claim
17 words
The memory cell of claim 1 wherein said first storage cell includes a first flash EEPROM cell.
Claim 4
Dependent Claim
17 words
The memory cell of claim 2 wherein said second storage cell includes a second flash EEPROM cell.
Claim 5
Dependent Claim
20 words
The memory cell of claim 3 wherein the first terminals of said first and second flash EEPROM cells are sources.
Claim 6
Dependent Claim
72 words
The memory cell of claim 1 further including a first transistor having a drain, a source, and a gate, and a second transistor having a drain, a source, and a gate, wherein the sources of said first and second transistors are connected to said first and second bitlines, respectively, and the drains of said first and second transistors are connected to the second terminals of said first and second storage cells, respectively.
Claim 7
Dependent Claim
20 words
The memory cell of claim 5 wherein the gates of said first and second transistors are connected to a wordline.
Claim 8
Dependent Claim
73 words
The memory cell of claim 6 wherein said means for forming includes a third transistor having a drain, a source, and a gate, and a fourth transistor having a drain, a source, and a gate, wherein the drains of said third and fourth transistors are connected to the second terminals of said first and second storage cells, respectively, and the gates of said third and fourth transistors are connected to a programming line.
Claim 9
Dependent Claim
57 words
The memory cell of claim 7 wherein said means for forming further includes a fifth transistor having a drain, a source, and a gate, and a sixth transistor having a drain, a source, and a gate, wherein the drains of said fifth and sixth transistors are connected to the sources of said third and fourth transistors, respectively.
Claim 10
Dependent Claim
25 words
The memory cell of claim 8 wherein the gates of said fifth and sixth transistors are connected to said first and second output lines, respectively.
Claim 11
Dependent Claim
21 words
The memory cell of claim 9 wherein the sources of said fifth and sixth transistors are connected to a voltage source.
Claim 12
Independent Claim
132 words
A method of providing a non-volatile memory cell including: providing a first non-volatile programmable and erasable storage cell, and a second non-volatile programmable and erasable storage cell; cross-coupling said first and second storage cells such that if said first storage cell is programmed, then said second storage cell is erased; providing a means to selectively program said first and second storage cells via a first bit line and a second bit line, respectively; and forming a latch including said first and second storage cells, a first transistor, and a second transistor, wherein the control terminals of said first storage cell and said first transistor are connected to a first output line, and wherein the control terminal of said second storage cell and said second transistor are connected to a second output line.
Claim 13
Independent Claim
132 words
A method of providing a non-volatile memory cell including: providing a first non-volatile programmable and erasable storage cell, and a second non-volatile programmable and erasable storage cell; cross-coupling said first and second storage cells such that if said first storage cell is programmed, then said second storage cell is erased; providing a means to selectively program said first and second storage cells via a first bit line and a second bit line, respectively; and forming a latch including said first and second storage cells, a first transistor, and a second transistor, wherein the control terminals of said first storage cell and said first transistor are connected to a first output line, and wherein the control terminal of said second storage cell and said second transistor are connected to a second output line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |