Patent US5523969A successfully refreshed from Google Patents.
US5523969A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically erasable programmable non-volatile semiconductor memory device and method for manufacturing the same
Assignee: Renesas Electronics Corp
•
Filing: 1994-10-06
•
Granted: 1996-06-04
•
Expires: 2014-10-06
Abstract
Abstract A flash memory includes a plurality of blocks each having a plurality of memory cells located at intersections between a plurality of row lines and at least one sub column line, and at least one main column line connected to said at least one sub column line of each of said blocks through a selection transistor. Both of said memory cells and said selection transistor have a floating gate electrode and a control gate electrode. The selection transistor has a drain region of the lightly doped drain structure in which a low impurity concentration diffused region is located at a channel side thereof.
Inventors
- 👤 Takeshi Okazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10B; H10B69/00; H10P; H10P10/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
106 words
A non-volatile semiconductor memory including: a plurality of blocks each having a plurality of memory cells located at intersections between a plurality of row lines and at least one sub column line; and at least one main column line connected to said at least one sub column line of each of said blocks through a selection transistor, both said memory cells and said selection transistor having a floating gate electrode and a control gate electrode, at least said selection transistor having a drain region which has a lightly doped drain structure in which a low impurity concentration diffused region is located at a channel side thereof.
Claim 2
Dependent Claim
106 words
A non-volatile semiconductor memory including: a plurality of blocks each having a plurality of memory cells located at intersections between a plurality of row lines and at least one sub column line; and at least one main column line connected to said at least one sub column line of each of said blocks through a selection transistor, both said memory cells and said selection transistor having a floating gate electrode and a control gate electrode, at least said selection transistor having a drain region which has a lightly doped drain structure in which a low impurity concentration diffused region is located at a channel side thereof.
Claim 3
Dependent Claim
26 words
A non-volatile semiconductor memory claimed in claim 1 wherein said low impurity concentration diffused region has a maximum impurity concentration of 10 19 cm -3 .
Claim 4
Dependent Claim
40 words
A non-volatile semiconductor memory claimed in claim 1 wherein in said selection transistor, a gate insulator film between said floating gate electrode and said control gate electrode is thicker than that between a channel surface and said floating gate electrode.
References Cited (Backward Citations)
US5218569A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |