US5523966A
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Memory cell and a memory device having reduced soft error
Assignee: Renesas Electronics Corp
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Filing: 1995-09-18
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Granted: 1996-06-04
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Expires: 2015-09-18
Abstract
Abstract Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C c between two data storage nodes 1 and 2. The p-well (or p-substrate) in which the driver-MOS transistors MN3, MN4 and the transfer MOS transistors MN1, MN2 are formed is connected to a V bb generator. The voltage V bb is set lower than the low level V L of the memory cell signal potential. Even when the potential variation ΔV L of the low-voltage side node 2 is large, the parasitic diode present between the n-type diffusion layer corresponding to the source or drain of MN1-MN4 and the p-well (or p-substrate) does not turn on. Erroneous operations can therefore be prevented.
Inventors
- 👤 Youji Idei
- 👤 Hiroaki Nambu
- 👤 Kazuo Kanetani
- 👤 Toru Masuda
- 👤 Kunihiko Yamaguchi
- 👤 Kenichi Ohhata
- 👤 Takeshi Kusunoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; H; H10; H10B; H10B10/00; H10B10/12
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
159 words
A memory cell for a static memory, comprising: two data storage nodes; a capacitor provided between said two data storage nodes; at least two MOS transistors which have their drains and sources formed in a conductive layer of a first conductivity type, and which have their gates and drains cross-connected to each other, said at least two MOS transistors being second conductivity type transistors, the second conductivity type being opposite to the first conductivity type; and a voltage generator for generating a first voltage, the voltage generator being electrically connected either to (a) the conductive layer of the first conductivity type, or to (b) the sources of the at least two MOS transistors, the other of (a) the conductive layer of the first conductivity type or (b) the sources of the at least two MOS transistors being electrically connected to a second voltage source different than the voltage generator, for supplying a second voltage different than the first voltage.
Claim 2
Dependent Claim
159 words
A memory cell for a static memory, comprising: two data storage nodes; a capacitor provided between said two data storage nodes; at least two MOS transistors which have their drains and sources formed in a conductive layer of a first conductivity type, and which have their gates and drains cross-connected to each other, said at least two MOS transistors being second conductivity type transistors, the second conductivity type being opposite to the first conductivity type; and a voltage generator for generating a first voltage, the voltage generator being electrically connected either to (a) the conductive layer of the first conductivity type, or to (b) the sources of the at least two MOS transistors, the other of (a) the conductive layer of the first conductivity type or (b) the sources of the at least two MOS transistors being electrically connected to a second voltage source different than the voltage generator, for supplying a second voltage different than the first voltage.
Claim 3
Dependent Claim
41 words
A memory cell according to claim 1, wherein the voltage generator is electrically connected to the conductive layer of the first conductivity type, and the sources of the at least two MOS transistors are electrically connected to the second voltage source.
Claim 4
Dependent Claim
17 words
A memory cell according to claim 2, wherein the second voltage source is a negative power supply.
Claim 5
Dependent Claim
36 words
A memory cell according to claim 2, wherein the first conductivity type is p-type, and wherein the first voltage is less than a power supply voltage of the second voltage source, on a low voltage side.
Claim 6
Dependent Claim
31 words
A memory cell according to claim 2, wherein the first conductivity type is n-type, and wherein the first voltage is higher than a power supply voltage on a high voltage side.
Claim 7
Dependent Claim
42 words
A memory cell according to claim 1, wherein a silicon dioxide layer is provided so as to isolate the first-conductivity type conductive layer from a first-conductivity type substrate thereunder, and also to isolate a first-conductivity-type MOS transistor from a second-conductivity-type MOS transistor.
Claim 8
Dependent Claim
49 words
A memory cell according to claim 1, wherein a highly doped layer of the second conductivity type is provided between a lower portion of the first conductivity-type conductive layer and a substrate of the first conductivity type, and the highly doped layer is connected to a power supply voltage.
Claim 9
Dependent Claim
32 words
A memory cell according to claim 7, wherein the highly doped layer is of n-conductivity-type, and wherein the highly doped layer is connected to a power supply voltage on a high-voltage side.
Claim 10
Dependent Claim
32 words
A memory cell according to claim 7, wherein the highly doped layer is of p-conductivity-type, and wherein the highly doped layer is connected to a power supply voltage on a low-voltage side.
Claim 11
Dependent Claim
52 words
A memory cell according to claim 1, wherein the voltage generator is electrically connected to the sources of the at least two MOS transistors, and wherein the conductive layer of the first conductivity type is electrically connected to the second voltage source for supplying the second voltage different than the first voltage.
Claim 12
Dependent Claim
30 words
A memory device comprising a plurality of the memory cells of claim 10, and peripheral circuits, the peripheral circuits including driver circuits, the driver circuits being emitter coupled logic circuits.
Claim 13
Dependent Claim
17 words
A memory cell according to claim 10, wherein the second voltage source is a power supply voltage.
Claim 14
Independent Claim
180 words
A method of reducing soft error in a static memory, the static memory having memory cells, each memory cell including (1) two data storage nodes, with a capacitance therebetween, and (2) at least two MOS transistors which have their drains and sources formed in a conductive layer of a first conductivity type, and which have their gates and drains cross-connected to each other, the at least two MOS transistors being second conductivity type transistors, the second conductivity type being opposite to the first conductivity type, the method comprising the steps of: applying a first voltage to the conductive layer of the first conductivity type, and applying a second voltage to the sources of the at least two MOS transistors, the second voltage being different from the first voltage, the first voltage being different from the second voltage such that a parasitic diode formed between the drain of one of the at least two MOS transistors and the first-conductivity-type conductive layer is not turned on by a voltage change in a data storage node caused by an alpha-ray induced noise current.
Claim 15
Independent Claim
180 words
A method of reducing soft error in a static memory, the static memory having memory cells, each memory cell including (1) two data storage nodes, with a capacitance therebetween, and (2) at least two MOS transistors which have their drains and sources formed in a conductive layer of a first conductivity type, and which have their gates and drains cross-connected to each other, the at least two MOS transistors being second conductivity type transistors, the second conductivity type being opposite to the first conductivity type, the method comprising the steps of: applying a first voltage to the conductive layer of the first conductivity type, and applying a second voltage to the sources of the at least two MOS transistors, the second voltage being different from the first voltage, the first voltage being different from the second voltage such that a parasitic diode formed between the drain of one of the at least two MOS transistors and the first-conductivity-type conductive layer is not turned on by a voltage change in a data storage node caused by an alpha-ray induced noise current.
Claim 16
Independent Claim
152 words
A method of reducing soft error in a static memory, the static memory having memory cells, each memory cell including (1) two data storage nodes, with a capacitance therebetween, and (2) at least two MOS transistors which have their drains and sources formed in a conductive layer of a first conductivity type, and which have their gates and drains cross-connected to each other, the at least two MOS transistors being second conductivity type transistors, the second conductivity type being opposite to the first conductivity type, the method comprising the steps of: applying a first voltage to the conductive layer of the first conductivity type, and applying a second voltage to the sources of the at least two MOS transistors, the second voltage being higher than the first voltage when the first conductivity type is p-type, and the second voltage is lower than the first voltage when the first conductivity type is n-type.
Claim 17
Independent Claim
152 words
A method of reducing soft error in a static memory, the static memory having memory cells, each memory cell including (1) two data storage nodes, with a capacitance therebetween, and (2) at least two MOS transistors which have their drains and sources formed in a conductive layer of a first conductivity type, and which have their gates and drains cross-connected to each other, the at least two MOS transistors being second conductivity type transistors, the second conductivity type being opposite to the first conductivity type, the method comprising the steps of: applying a first voltage to the conductive layer of the first conductivity type, and applying a second voltage to the sources of the at least two MOS transistors, the second voltage being higher than the first voltage when the first conductivity type is p-type, and the second voltage is lower than the first voltage when the first conductivity type is n-type.
Claim 18
Dependent Claim
29 words
A method according to claim 14, wherein the first conductivity type is p-type, and wherein the first voltage is less than the second voltage, on the low voltage side.
Claim 19
Dependent Claim
30 words
A method according to claim 14, wherein the first conductivity type is n-type, and wherein the first voltage is higher than the power supply voltage on a high voltage side.
Claim 20
Dependent Claim
112 words
A method according to claim 14, wherein the first conductivity type is p-type, the second conductivity type is n-type, and the voltage level (V bb ) of the first-conductivity-type conductive layer is so set as to satisfy the condition of the following expression: ##EQU8## where V L stands for a low level of signal level of the memory cell, C 2 for a capacitance between one of the data storage nodes of the memory cell and ground, C 3 for a coupling capacitance between the two data storage nodes, V s for a signal amplitude of the memory cell, and V F for a voltage at which the parasitic diode turns on.
Claim 21
Dependent Claim
112 words
A method according to claim 14, wherein the first conductivity type is n-type, the second conductivity type is p-type, and the voltage level (V bb ) of the first-conductivity-type conductive layer is so set as to satisfy the condition of the following expression: ##EQU9## where V H stands for a high level of signal level of the memory cell, C 2 for a capacitance between one of the data storage nodes of the memory cell and ground, C 3 for a coupling capacitance between the two data storage nodes, V S for a signal amplitude of the memory cell, and V F for a voltage at which the parasitic diode turns on.
Claim 22
Dependent Claim
42 words
A method according to claim 14, wherein the voltage (V bb ) of the first-conductivity-type conductive layer of each of the memory cells is set below a power supply voltage (V EE ) on a low voltage side of the static memory.
Claim 23
Dependent Claim
43 words
A method according to claim 14, wherein a low level (V L ) Of the signal level of each of the memory cells is set above a power supply voltage (V EE ) on a low voltage side of the static memory device.
Claim 24
Dependent Claim
39 words
A method according to claim 14, wherein the voltage (V bb ) of the first-conductivity-type conductive layer of each of the memory cells is set above a power supply voltage on a high voltage side of the static memory.
Claim 25
Dependent Claim
39 words
A method according to claim 14, wherein the high level (V H ) of the signal level of each of the memory cells is set below a power supply voltage on a high voltage side of the static memory.
Claim 26
Dependent Claim
209 words
A memory cell for a static memory, comprising: two data storage nodes, the two data storage nodes having a capacitance therebetween; at least two MOS transistors which have their drains and sources formed in a conductive layer of a first conductivity type, and which have their gates and drains cross-connected to each other, said at least two MOS transistors being second conductivity type transistors, the second conductivity type being opposite to the first conductivity type; and a voltage generator for generating a first voltage, the voltage generator being electrically connected to (a) the conductive layer of the first conductivity type, or to (b) the sources of the at least two MOS transistors, the other of (a) the conductive layer of the first conductivity type or (b) the sources of the at least two MOS transistors being electrically connected to a second voltage source different than the voltage generator, for supplying a second voltage different than the first voltage, wherein the first voltage is set to a voltage level at which a parasitic diode formed between a drain of one of the second-conductivity-type-MOS transistors and the first conductivity-type conductive layer is not turned on by a voltage change in a data storage node caused by an alpha-ray induced noise current.
Claim 27
Dependent Claim
209 words
A memory cell for a static memory, comprising: two data storage nodes, the two data storage nodes having a capacitance therebetween; at least two MOS transistors which have their drains and sources formed in a conductive layer of a first conductivity type, and which have their gates and drains cross-connected to each other, said at least two MOS transistors being second conductivity type transistors, the second conductivity type being opposite to the first conductivity type; and a voltage generator for generating a first voltage, the voltage generator being electrically connected to (a) the conductive layer of the first conductivity type, or to (b) the sources of the at least two MOS transistors, the other of (a) the conductive layer of the first conductivity type or (b) the sources of the at least two MOS transistors being electrically connected to a second voltage source different than the voltage generator, for supplying a second voltage different than the first voltage, wherein the first voltage is set to a voltage level at which a parasitic diode formed between a drain of one of the second-conductivity-type-MOS transistors and the first conductivity-type conductive layer is not turned on by a voltage change in a data storage node caused by an alpha-ray induced noise current.
Claim 28
Dependent Claim
41 words
A memory cell according to claim 23, wherein the voltage generator is electrically connected to the conductive layer of the first conductivity type, and the sources of the at least two MOS transistors are electrically connected to the second voltage source.
Claim 29
Dependent Claim
17 words
A memory cell according to claim 24, wherein the second voltage source is a negative power supply.
Claim 30
Dependent Claim
37 words
A memory cell according to claim 24, wherein the first voltage conductivity type is p-type, and wherein the first voltage is less than a power supply voltage of the second voltage source, on a low voltage side.
Claim 31
Dependent Claim
31 words
A memory cell according to claim 24, wherein the first conductivity type is n-type, and wherein the first voltage is higher than a power supply voltage on a high voltage side.
Claim 32
Dependent Claim
32 words
A memory cell according to claim 23, wherein the two data storage nodes are provided such that a parasitic capacitance is provided between the two data storage nodes, as the capacitance therebetween.
Claim 33
Dependent Claim
49 words
A memory cell according to claim 23, wherein a highly doped layer of the second conductivity type is provided between a lower portion of the first conductivity-type conductive layer and a substrate of the first conductivity type, and the highly doped layer is connected to a power supply voltage.
References Cited (Backward Citations)
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