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US5523710A Expired / Lapsed US ⏱️ 0.0 years remaining

Initial value setting circuit

Assignee: Panasonic Holdings Corp
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Filing: 1995-05-16
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Granted: 1996-06-04
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Expires: 2015-05-16
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Abstract

Abstract A voltage level of an output node is reversed by an inverter. An output of the inverter is used as an initial setting signal. A feedback switching transistor is also provided in an initial value setting circuit. Furthermore, there is provided a limiting device for eliminating an abnormal operation of the feedback switching transistor until the inverter starts a normal operation, in the event of momentary power failure or when the electric power source is quickly turned on after a very short break. Accordingly, normal operation of the inverter is assured even in such an abnormal condition accompanying momentary interruption of power supply, thereby surely outputting an initial setting signal.

Inventors

  • 👤 Naomi Miyake
  • 👤 Makoto Kojima

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 17:46
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 172 words
An initial value setting circuit comprising: an output node; a capacitor for setting a voltage level of said output node to a predetermined initial setting level; an initial-condition-reset switching means, controlled by an initial-condition-reset signal supplied from an external device, for setting the voltage level of said output node to another setting level different from said predetermined initial setting level; an inverter having an input stage connected to said output node and an output stage generating a voltage level opposed to the voltage level of said output node; a feedback switching means, controlled by an output of said inverter, for maintaining the voltage level of said output node; and a limiting means for limiting operations of said initial-condition-reset switching means and said feedback switching means until a voltage level of an electric power source reaches a predetermined threshold level assuring a normal operation of said inverter, when the voltage level of the electric power source is increased up to a specified value in response to turning-on operation of said electric power source.
Claim 2
Dependent Claim 172 words
An initial value setting circuit comprising: an output node; a capacitor for setting a voltage level of said output node to a predetermined initial setting level; an initial-condition-reset switching means, controlled by an initial-condition-reset signal supplied from an external device, for setting the voltage level of said output node to another setting level different from said predetermined initial setting level; an inverter having an input stage connected to said output node and an output stage generating a voltage level opposed to the voltage level of said output node; a feedback switching means, controlled by an output of said inverter, for maintaining the voltage level of said output node; and a limiting means for limiting operations of said initial-condition-reset switching means and said feedback switching means until a voltage level of an electric power source reaches a predetermined threshold level assuring a normal operation of said inverter, when the voltage level of the electric power source is increased up to a specified value in response to turning-on operation of said electric power source.
Claim 3
Dependent Claim 78 words
The initial value setting circuit defined by claim 1, wherein said limiting means functions as said initial-condition-reset switching means, and said limiting means limits the operation of said feedback switching means until the voltage level of the electric power source reaches the predetermined threshold level assuring a normal operation of said inverter, when the voltage level of the electric power source is increased up to the specified value in response to turning-on operation of said electric power source.
Claim 4
Dependent Claim 63 words
The initial value setting circuit defined by claim 1, wherein said limiting means is connected to the electric power source, and is activated when the voltage level of the electric power source reaches the predetermined threshold level assuring a normal operation of said inverter, thereby applying the voltage of said electric power source to said feedback switching means and said initial-condition-reset switching means.
Claim 5
Dependent Claim 58 words
The initial value setting circuit defined by claim 2, wherein said limiting means is connected to the electric power source, and is activated when the voltage level of the electric power source reaches the predetermined threshold level assuring a normal operation of said inverter, thereby applying the voltage of said electric power source to said feedback switching means.
Claim 6
Dependent Claim 73 words
The initial value setting circuit defined by claim 3 or 4, wherein said limiting means comprises a current mirror circuit consisting of a pair of MOS transistors connected to the electric power source, and at least one conductive-voltage-setting MOS transistor connected to one MOS transistor of said current mirror circuit, for determining a boundary voltage of turning-on and off the other MOS transistor of said current mirror circuit connected to an output terminal.
Claim 7
Dependent Claim 33 words
The initial value setting circuit defined by claim 3 or 4, wherein said limiting means is connected to another capacitor for assuring a smooth building-up of an output voltage of said limiting means.
Claim 8
Dependent Claim 59 words
The initial value setting circuit defined by claim 1, 2, 3 or 4, wherein said feedback switching means is constituted by a MOS transistor, and another MOS transistor is interposed between said output node and the electric power source, said another MOS transistor having a threshold voltage lower than that of the MOS transistor constituting said feedback switching means.

References Cited (Backward Citations)

JPS62169022A Cited
JPS63285033A Cited
US5450417A Cited
US5467037A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-06-04 1999-12-04 2000-06-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-06-04 2003-12-04 2004-06-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-06-04 2007-12-04 2008-06-04 $7700.00 Window Closed / Lapsed

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