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US5523587A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for low temperature growth of epitaxial silicon and devices produced thereby

Assignee: AT&T Inc
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Filing: 1993-06-24
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Granted: 1996-06-04
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Expires: 2013-06-24
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Abstract

Abstract In accordance with the invention, a thin layer of epitaxial silicon is grown at low temperatures at or below 300° C. by the steps of providing a substrate, forming an oriented dielectric buffer layer on the substrate and growing epitaxial silicon on the buffer layer. Preferably the substrate has a glass surface and the oriented buffer layer is cubic ZrO 2 . The buffer layer is preferably oriented by bombarding it with a directed ion beam while the buffer layer is being deposited on the substrate. For example, a buffer layer of (100) cubic ZrO 2 can be grown at a temperature as low as 300° C. The oriented cubic ZrO 2 is an excellent buffer for epitaxial silicon on glass due to a good match of lattice parameters with silicon and a good match of thermal expansion coefficients with glass. An oriented (100) silicon epitaxial film can then be grown on the epitaxial template provided by the buffer layer at a temperature as low as 250° C. This low temperature process for producing epitaxial films offers multiple advantages: (1) reduced silicon interfacial defect densities and enlarged grain size permitting improved thin film transistor performance due to a lowered "off" current; (2) higher electron mobility permitting the fabrication of integrated displays; (3) lower temperature processing permitting the use of inexpensive glass substrates such as borosilicates; (4) sufficiently low temperature processing to permit the use of new lightweight substrates such as glass-coated polymeric materials (glass-coated plastics) which can substantially reduce the weight of displays and thus enhance the portability of portable computers, video telephones, and personal communicators; and (5) the use of new buffer layers such as ZrO 2 which can block the diffusion of Na ions from the substrate.

Inventors

  • 👤 Jueinai R. Kwo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 15:22
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2922; H10P14/22; H10P14/24; H10P14/32; H10P14/3202; H10P14/3238; H10P14/3258; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; Y; Y10; Y10S; Y10S438/00; Y10S438/967

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 48 words
A silicon device comprising: a substrate comprising a body of material having a planar major surface and a layer of glass overlying said major surface; overlying said glass layer a (100) oriented buffer layer of dielectric material; and overlying said buffer layer a (100) oriented layer of silicon.
Claim 2
Dependent Claim 48 words
A silicon device comprising: a substrate comprising a body of material having a planar major surface and a layer of glass overlying said major surface; overlying said glass layer a (100) oriented buffer layer of dielectric material; and overlying said buffer layer a (100) oriented layer of silicon.
Claim 3
Dependent Claim 14 words
A device according to claim 1 wherein said substrate is transparent to visible light.
Claim 4
Dependent Claim 15 words
A device according to claim 1 wherein said body comprises a body of polymeric material.
Claim 5
Dependent Claim 16 words
A device according to claim 3 wherein said polymeric material is a polyimide or a polyethersulfone.
Claim 6
Dependent Claim 23 words
A device according to claim 1 wherein said buffer layer comprises ZrO 2 ,CeO 2 ,PRO 2 or Y 2 O 3 .
Claim 7
Dependent Claim 83 words
A thin film transistor comprising a source, a gate-controlled channel and a drain disposed upon a substrate having a planar major surface wherein said source, channel and drain comprise a layer of (100) oriented silicon overlying said planar major surface and said substrate comprises a body of polymeric material and a layer of glass overlying said body of polymeric material, said transistor further comprising a buffer layer of (100) oriented dielectric material disposed between said layer of glass and said layer of silicon.
Claim 8
Dependent Claim 83 words
A thin film transistor comprising a source, a gate-controlled channel and a drain disposed upon a substrate having a planar major surface wherein said source, channel and drain comprise a layer of (100) oriented silicon overlying said planar major surface and said substrate comprises a body of polymeric material and a layer of glass overlying said body of polymeric material, said transistor further comprising a buffer layer of (100) oriented dielectric material disposed between said layer of glass and said layer of silicon.
Claim 9
Dependent Claim 48 words
A liquid crystal display comprising a common electrode, a liquid crystal medium, and a plurality of transistor-controlled local electrodes for controlling local regions of the liquid crystal medium wherein one or more of the transistors for controlling said local electrodes comprises a transistor in accordance with claim 6.

References Cited (Backward Citations)

US5306651A Cited
US5304357A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-06-04 1999-12-04 2000-06-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-06-04 2003-12-04 2004-06-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-06-04 2007-12-04 2008-06-04 $7700.00 Window Closed / Lapsed

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