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US5523251A
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Method for fabricating a self aligned mask ROM
Assignee: United Microelectronics Corp
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Filing: 1994-10-05
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Granted: 1996-06-04
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Expires: 2014-10-05
Abstract
Abstract A method of manufacturing mask ROM using LPD to obtain the advantages of self-alignment. The bit line resistance and bit line capacitance are both reduced due to prevention of counterdoping but the device breakdown voltage is maintained. Oxide regions are deposited over the bit lines by LPD to form mesas thereon. When a conductive layer is deposited, recesses in the conductive layer occur in channel regions between neighboring mesas. When programming the device by implanting impurities, they automatically concentrate in the channel regions between the bit lines, in a self-aligned manner, therefore counterdoping of the bit lines is prevented.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:13
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
141 words
A method of fabricating a mask ROM on a semiconductor substrate, the mask ROM having bit lines and word lines, which comprises the following steps: (a) forming a gate oxide on the substrate; (b) forming a first conductive layer on said gate oxide; (c) forming a mask layer on said first conductive layer; (d) etching said mask layer and said first conductive layer using a bit line mask; (e) implanting impurities into the substrate to form the bit lines of the mask ROM; (f) depositing an oxide layer on said gate oxide to form oxide regions having a thickness greater than a thickness of the first conductive layer; (g) removing said mask layer; (h) forming a second conductive layer thereon; and (i) etching said second conductive layer and said first conductive layer to form the word lines of the mask ROM.
Claim 2
Independent Claim
141 words
A method of fabricating a mask ROM on a semiconductor substrate, the mask ROM having bit lines and word lines, which comprises the following steps: (a) forming a gate oxide on the substrate; (b) forming a first conductive layer on said gate oxide; (c) forming a mask layer on said first conductive layer; (d) etching said mask layer and said first conductive layer using a bit line mask; (e) implanting impurities into the substrate to form the bit lines of the mask ROM; (f) depositing an oxide layer on said gate oxide to form oxide regions having a thickness greater than a thickness of the first conductive layer; (g) removing said mask layer; (h) forming a second conductive layer thereon; and (i) etching said second conductive layer and said first conductive layer to form the word lines of the mask ROM.
Claim 3
Dependent Claim
38 words
A method of fabricating a mask ROM on a semiconductor substrate as claimed in claim 1, further including the step of implanting impurities into regions of the substrate via said first conductive layer and said second conductive layer.
Claim 4
Dependent Claim
28 words
A method of fabricating a mask ROM on a semiconductor substrate as claimed in claim 1, wherein step (f) further comprises forming sidewall spacers beside said oxide regions.
Claim 5
Dependent Claim
22 words
A method of fabricating a mask ROM on a semiconductor substrate as claimed in claim 3, wherein said sidewall spacers comprise oxide.
Claim 6
Dependent Claim
22 words
A method of fabricating a mask ROM on a semiconductor substrate as claimed in claim 3, wherein said sidewall spacers comprise nitride.
Claim 7
Dependent Claim
29 words
A method of fabricating a mask ROM on a semiconductor substrate as claimed in claim 1, wherein said first conductive layer and said second conductive layer both comprise polysilicon.
Claim 8
Dependent Claim
30 words
A method of fabricating a mask ROM on a semiconductor substrate as claimed in claim 1, wherein said first conductive layer comprises polysilicon and said second conductive layer comprises silicide.
References Cited (Backward Citations)
US5308777A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |