Process for fabricating high-performance facet-free small-sized bipolar transistor

Claim 2

A process of fabricating a semiconductor device on a collector layer of a first conductivity type defined by an isolating region, comprising the steps of: a) successively depositing a first insulating layer, a polysilicon base electrode layer of a second conductivity type and a second insulating layer selective from said first insulating layer in an etchant over said collector layer; b) partially etching said second insulating layer and said polysilicon base electrode layer for forming an emitter hole over a central area of said collector layer; c) depositing an insulating material selective from said first insulating layer in said etchant on said second insulating layer, an inner peripheral wall defining said emitter hole and an area of said first insulating layer exposed to said emitter hole; d) forming a first side wall on said inner peripheral wall defining said emitter hole from said insulating material by using an etching back technique; e) partially etching said first insulating layer for exposing a part of said collector layer and forming a hollow space beneath said polysilicon base electrode layer, said hollow space having a lateral length; f) depositing a silicon selected from the group consisting of polysilicon and amorphous silicon on said second insulating layer, said first side wall and said part of said collector layer so as to fill said hollow space; g) etching said silicon in such a manner that a piece of said polysilicon or said amorphous silicon is left in said hollow space; and h) epitaxially growing a base layer of said second conductivity type on an exposed area of said collector layer.

Claim 3

A process of fabricating a semiconductor device having a bipolar transistor, comprising the steps of: a) preparing a substrate having a collector region of a first conductivity type defined by an isolating region; b) successively depositing a first insulating layer of a first insulating material, a base electrode layer of a first semiconductor material and a second insulating layer of a second insulating material selective to said first insulating material in an etchant over at least said collector region; c) forming an emitter hole in said second insulating layer and said base electrode layer so as to expose a central area of said first insulating layer; d) forming a first side wall of a third insulating material on an inner periphery of said base electrode layer defining said emitter hole, said third insulating material being selective to said first insulating material in said etchant; e) etching said central area and a peripheral area of said first insulating layer by using said etchant so as to form a hollow space beneath an inner peripheral portion of said base electrode layer, said hollow space being contiguous to said emitter hole reaching a central area of said collector region; f) filling said hollow space with a second semiconductor material, said step f) including the sub-steps of f-1) depositing said second semiconductor material over the entire surface so as to fill said hollow space, f-2) etching layer of said second semiconductor material through an isotropical dry etching technique by using said second insulating layer and said first side wall as a mask so that a piece of said second semiconductor material is left in said hollow space; g) selectively growing a base layer of a second conductivity type formed of a third semiconductor material on said central area of said collector region, said base layer being merged with said second semiconductor material without a facet; and h) forming an emitter region of said first conductivity type in said base layer.

Claim 4

A process of fabricating a semiconductor device having a bipolar transistor, comprising the steps of: a) preparing a substrate having a collector region of a first conductivity type defined by an isolating region; b) successively depositing a first insulating layer of a first insulating material, a base electrode layer of a first semiconductor material and a second insulating layer of a second insulating material selective to said first insulating material in an etchant over at least said collector region; c) forming an emitter hole in said second insulating layer and said base electrode layer so as to expose a central area of said first insulating layer; d) forming a first side wall of a third insulating material on an inner periphery of said base electrode layer defining said emitter hole, said third insulating material being selective to said first insulating material in said etchant; e) etching said central area and a peripheral area of said first insulating layer by using said etchant so as to form a hollow space beneath an inner peripheral portion of said base electrode layer, said hollow space being contiguous to said emitter hole reaching a central area of said collector region; f) filling said hollow space with a second semiconductor material, said step f) including the sub-steps of f-1) depositing said second semiconductor material over the entire surface so as to fill said hollow space, f-2) etching layer of said second semiconductor material through an isotropical dry etching technique by using said second insulating layer and said first side wall as a mask so that a piece of said second semiconductor material is left in said hollow space; g) selectively growing a base layer of a second conductivity type formed of a third semiconductor material on said central area of said collector region, said base layer being merged with said second semiconductor material without a facet; and h) forming an emitter region of said first conductivity type in said base layer.

Claim 5

The process as set forth in claim 2, in which said first insulating material, said first semiconductor material, said second insulating material and said third insulating material are a silicon oxide, a polysilicon doped with impurity atoms of said second conductivity type, a silicon nitride and a silicon nitride, respectively.

Claim 6

The process as set forth in claim 2, in which said first insulating layer has a thickness ranging from 40 nanometers to 140 nanometers depending upon a thickness of said base layer.

Claim 7

The process as set forth in claim 2, in which said step d) comprises the sub-steps of d-1) depositing said third insulating material over the entire surface for forming a third insulating layer, and d-2) anisotropically etching said third insulating layer so as to form said first side wall.

Claim 8

The process as set forth in claim 2, in which a wet etching technique is used for etching said central area and a peripheral area of said first insulating layer in said step e).

Claim 9

The process as set forth in claim 2, in which said second semiconductor material is a non-doped polysilicon, said process further comprising the step of diffusing impurity from said base electrode layer into said piece of second semiconductor material between said step f) and said step g).

Claim 10

The process as set forth in claim 2, in which said second semiconductor material is a polysilicon doped with impurity atoms of said second conductivity type.

Claim 11

The process as set forth in claim 2, in which said second semiconductor material is an amorphous silicon, said process further comprising the step of a heat treatment between said step f) and said step g) for converting said amorphous silicon to a polysilicon.

Claim 12

The process as set forth in claim 9, in which said amorphous silicon is doped with impurity atoms of said second conductivity type.

Claim 13

The process as set forth in claim 2, in which said second semiconductor material is a silicon-germanium.

Claim 14

The process as set forth in claim 2, in which said third semiconductor material is grown through one of a ultra high vacuum chemical vapor deposition and a molecular beam epitaxy.

Claim 15

The process as set forth in claim 12, in which said third semiconductor material is selected from the group consisting of a doped single crystal silicon, a silicon-germanium.

Claim 16

The process as set forth in claim 2, in which said step h) comprises the sub-steps of h-1) depositing a fourth semiconductor material doped with impurity atoms of said first conductivity type over the entire surface, a part of a layer of said fourth semiconductor material being held in contact with a part of said base layer, h-2) patterning said layer of said fourth semiconductor material into an emitter electrode, and h-3) applying heat to said emitter electrode so as to diffuse impurity atoms of said first conductivity type into said part of said base layer, thereby forming said emitter region.

Claim 17

The process as set forth in claim 2, in which said emitter region is grown by using one of an ultra high vacuum chemical vapor deposition and a molecular beam epitaxy.

Claim 18

The process as set forth in claim 15, in which said fourth semiconductor material is selected from the group consisting of a doped silicon and doped silicon carbide.