Patent US5521870A successfully refreshed from Google Patents.
US5521870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device having a coincidence detection circuit and its test method
Assignee: PS4 Luxco SARL
•
Filing: 1994-12-06
•
Granted: 1996-05-28
•
Expires: 2014-12-06
Abstract
Abstract A semiconductor memory device includes a plurality of memory blocks, a write circuit for writing data into the memory blocks, a read circuit for reading data from the memory blocks, a plurality of serial registers, each of which is connected to the corresponding memory block to output serially a plurality of data read from the memory block, a plurality of switches, each of which is arranged between two adjacent ones of the serial registers to connect the serial registers in series, and a coincidence detection circuit for detecting a coincidence of data outputted from a final serial register arranged at a final end of the serial registers connected by the switches with data outputted from a serial register arranged immediately before the final serial register.
Inventors
- 👤 Toru Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:04
CPC Classifications
G; G11; G11C; G11C29/00; G11C7/00; G11C7/10; G11C7/1015; G11C7/1036; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/32; G11C29/38; G11C29/40; G11C2029/4002
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
126 words
A semiconductor memory device comprising: a plurality of memory blocks; a write circuit for writing data into said memory blocks; a read circuit for reading data from said memory blocks; a plurality of serial registers, each of said serial registers being connected to a corresponding memory block to output serially a plurality of data read from the memory block; a plurality of switches, each of said switches being arranged between two adjacent ones of said serial registers to connect said serial registers in series; and coincidence detection means for detecting a coincidence of data outputted from a final serial register arranged at a final end of said serial registers connected by said switches with data outputted from a serial register arranged before said final serial register.
Claim 2
Dependent Claim
126 words
A semiconductor memory device comprising: a plurality of memory blocks; a write circuit for writing data into said memory blocks; a read circuit for reading data from said memory blocks; a plurality of serial registers, each of said serial registers being connected to a corresponding memory block to output serially a plurality of data read from the memory block; a plurality of switches, each of said switches being arranged between two adjacent ones of said serial registers to connect said serial registers in series; and coincidence detection means for detecting a coincidence of data outputted from a final serial register arranged at a final end of said serial registers connected by said switches with data outputted from a serial register arranged before said final serial register.
Claim 3
Dependent Claim
21 words
The semiconductor memory device as defined in claim 1 wherein each of said plurality of switches comprises an N-channel transfer gate.
Claim 4
Dependent Claim
20 words
The semiconductor memory device as defined in claim 1 wherein said coincidence detection means includes a 2-input exclusive NOR circuit.
Claim 5
Dependent Claim
54 words
The semiconductor memory device as defined in claim 1 wherein said plurality of serial registers include a plurality of D-type flip flops and a plurality of transfer gates respectively, each of said transfer gates being arranged between two adjacent D-type flip flops to connect the D-type flip flops in series in a test mode.
Claim 6
Dependent Claim
110 words
A semiconductor memory device comprising: a plurality of memory blocks (=n blocks); a plurality of n serial registers, each of said serial registers being connected to a corresponding memory block to output serially a plurality of data read from the memory block; a plurality of switches for connecting said n serial registers by every m serial registers in series; and a plurality of coincidence detection circuits, wherein each of said coincidence detection circuits is arranged to detect a coincidence of data outputted from a final serial register of the m serial registers connected by the switches with data outputted from a serial register arranged immediately before the final serial register.
Claim 7
Dependent Claim
110 words
A semiconductor memory device comprising: a plurality of memory blocks (=n blocks); a plurality of n serial registers, each of said serial registers being connected to a corresponding memory block to output serially a plurality of data read from the memory block; a plurality of switches for connecting said n serial registers by every m serial registers in series; and a plurality of coincidence detection circuits, wherein each of said coincidence detection circuits is arranged to detect a coincidence of data outputted from a final serial register of the m serial registers connected by the switches with data outputted from a serial register arranged immediately before the final serial register.
Claim 8
Dependent Claim
19 words
The semiconductor memory device as defined in claim 5 wherein said plurality of switches comprises an N-channel transfer gate.
Claim 9
Dependent Claim
22 words
The semiconductor memory device as defined in claim 5 wherein each of said coincidence detection circuits includes a 2-input exclusive NOR circuit.
Claim 10
Dependent Claim
51 words
The semiconductor memory device as defined in claim 5 wherein the serial register includes a plurality of D-type flip flops and a plurality of transfer gates, each of said transfer gates being arranged between two adjacent D-type flip flops to connect the D-type flip flops in series in a test mode.
Claim 11
Independent Claim
140 words
A method for testing a semiconductor memory, wherein said semiconductor memory device comprises a plurality of memory blocks, a write circuit for writing data into said memory blocks, a read circuit for reading data from said memory blocks, a plurality of n serial registers, each of said n serial registers being connected to a corresponding memory block to output serially data read from the memory block, the method comprising steps of: writing same data in said memory blocks at a test; inputting data read from said memory blocks to said serial registers; shifting the data in said n serial registers sequentially; and monitoring a result of a coincidence detection of data outputted from a final serial register arranged at a final end of said serial registers with a data outputted from a serial register arranged before the final serial register.
Claim 12
Independent Claim
140 words
A method for testing a semiconductor memory, wherein said semiconductor memory device comprises a plurality of memory blocks, a write circuit for writing data into said memory blocks, a read circuit for reading data from said memory blocks, a plurality of n serial registers, each of said n serial registers being connected to a corresponding memory block to output serially data read from the memory block, the method comprising steps of: writing same data in said memory blocks at a test; inputting data read from said memory blocks to said serial registers; shifting the data in said n serial registers sequentially; and monitoring a result of a coincidence detection of data outputted from a final serial register arranged at a final end of said serial registers with a data outputted from a serial register arranged before the final serial register.
Claim 13
Independent Claim
141 words
A method for testing a semiconductor memory, wherein said semiconductor memory device comprises a plurality of memory blocks, a plurality of serial registers, each of said serial registers being connected to a corresponding memory block to output serially data read from the memory block, said method comprising steps of: writing same data in said memory blocks at a test; inputting data read from said memory blocks to said serial registers; dividing said n serial registers into a plurality of groups, each group comprising m serial registers to connect said m serial registers in every group; and monitoring by every group of said groups a result of a coincidence detection of data outputted from a final serial register arranged at a final end of said m serial registers with data outputted from a serial register arranged immediately before the final serial register.
Claim 14
Independent Claim
141 words
A method for testing a semiconductor memory, wherein said semiconductor memory device comprises a plurality of memory blocks, a plurality of serial registers, each of said serial registers being connected to a corresponding memory block to output serially data read from the memory block, said method comprising steps of: writing same data in said memory blocks at a test; inputting data read from said memory blocks to said serial registers; dividing said n serial registers into a plurality of groups, each group comprising m serial registers to connect said m serial registers in every group; and monitoring by every group of said groups a result of a coincidence detection of data outputted from a final serial register arranged at a final end of said m serial registers with data outputted from a serial register arranged immediately before the final serial register.
References Cited (Backward Citations)
US4667313A
Cited
US5371714A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-28 | 1999-11-27 | 2000-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-28 | 2003-11-27 | 2004-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-28 | 2007-11-27 | 2008-05-28 | $7700.00 | Window Closed / Lapsed |