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US5519877A
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Apparatus for synchronizing parallel processing among a plurality of processors
Assignee: Panasonic Holdings Corp
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Filing: 1994-01-12
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Granted: 1996-05-21
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Expires: 2014-01-12
Abstract
Abstract Disclosed is an apparatus of synchronizing parallel processing among a plurality of processors including a plurality of synchronization units respectively corresponding to the plurality of processors and a control unit. The control unit and the synchronization units are connected in a loop. Each synchronization unit outputs a sync signal for informing that the synchronization unit has entered a wait state to an adjacent downstream unit. The control unit outputs a pulse for informing a completion of a synchronization among the processors to an uppermost-stream synchronization unit. The pulse is forwarded as far as an lowermost-stream synchronization unit. Each synchronization unit includes the following: a flag hold unit holding a flag indicating a state of a respective processor, a logical OR circuit ORing a sync signal sent from an adjacent upstream synchronization unit with a value of the flag and outputting an obtained value to an adjacent downstream synchronization unit as a sync signal, a detection unit detecting the pulse in a value outputted from the logical OR circuit, thereby initiating the flag hold unit, and an output unit outputting the value outputted from the logical OR circuit to a respective processor.
Inventors
- 👤 Yasushi Yoneda
- 👤 Shinichi Saeki
- 👤 Noriyuki Hidaka
- 👤 Minobu Abe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:58
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/52
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
214 words
An apparatus for synchronizing parallel processing among a plurality of processors, comprising: a control unit; and a plurality of synchronization units corresponding to said plurality of processors, respectively, said control unit and said synchronization units being connected in a loop, wherein each of said synchronization units outputs a synchronization signal for informing that said each synchronization unit has entered a wait state to a respective adjacent downstream unit; and said control unit outputs a pulse for informing a completion of synchronization among said processors to an uppermost-stream synchronization unit, said pulse being forwarded as far as a lowermost-stream synchronization unit, wherein each of said synchronization units comprises: a flag hold means for holding a flag indicating a state of a respective one of said processors; a logical OR means for ORing a said synchronization signal sent from an adjacent upstream synchronization unit with a value of said flag and for outputting an obtained value to an adjacent downstream synchronization unit as a said synchronization signal; a detection means for detecting said pulse outputted by said control unit in said synchronization signal outputted from said logical OR means, thereby initializing said flag hold means; and an output means for outputting said value outputted from said logical OR means to a respective one of said processors.
Claim 2
Independent Claim
214 words
An apparatus for synchronizing parallel processing among a plurality of processors, comprising: a control unit; and a plurality of synchronization units corresponding to said plurality of processors, respectively, said control unit and said synchronization units being connected in a loop, wherein each of said synchronization units outputs a synchronization signal for informing that said each synchronization unit has entered a wait state to a respective adjacent downstream unit; and said control unit outputs a pulse for informing a completion of synchronization among said processors to an uppermost-stream synchronization unit, said pulse being forwarded as far as a lowermost-stream synchronization unit, wherein each of said synchronization units comprises: a flag hold means for holding a flag indicating a state of a respective one of said processors; a logical OR means for ORing a said synchronization signal sent from an adjacent upstream synchronization unit with a value of said flag and for outputting an obtained value to an adjacent downstream synchronization unit as a said synchronization signal; a detection means for detecting said pulse outputted by said control unit in said synchronization signal outputted from said logical OR means, thereby initializing said flag hold means; and an output means for outputting said value outputted from said logical OR means to a respective one of said processors.
Claim 3
Dependent Claim
82 words
The apparatus of claim 1, wherein said flag has a value of one of a logical one and a logical zero, said logical one indicating that a respective one of said processors is in operation and said logical zero indicating that a respective one of said processor is in a wait state, and said control means detects a change from said logical one to said logical zero, thereby outputting said pulse, said pulse being a logical one pulse with a fixed width.
Claim 4
Dependent Claim
39 words
The apparatus of claim 2, wherein said control means comprises a negative edge-triggered single shot circuit for outputting said logical one pulse when a negative edge is detected in a said synchronization signal sent from said lowermost-stream synchronization unit.
Claim 5
Dependent Claim
49 words
The apparatus of claim 3, wherein said logical OR means comprises an OR gate for receiving a said synchronization signal from an adjacent upstream synchronization unit and a value of said flag and for outputting a logical OR to an adjacent downstream synchronization unit as a said synchronization signal.
Claim 6
Dependent Claim
29 words
The apparatus of claim 4, wherein said flag hold means comprises a flip-flop for holding a value of said flag and for outputting said value to said OR gate.
Claim 7
Dependent Claim
73 words
The apparatus of claim 5, wherein said detection means comprises a positive edge triggered single shot circuit for outputting said pulse to said flip-flop when a positive edge is detected in a said logical OR outputted from said OR gate, and wherein said flip-flop comprises a set terminal for receiving an output of said positive edge triggered single shot circuit, said set terminal being set a logical one by said logical one pulse.
Claim 8
Dependent Claim
44 words
The apparatus of claim 6, wherein said output means comprises a tri-state buffer for receiving said logical OR from said logical OR means and for outputting an obtained value under a control of a read signal sent from a respective one of said processors.
Claim 9
Dependent Claim
39 words
The apparatus of claim 6, wherein said output means comprises an interrupt generation circuit for detecting said positive edge in the logical OR and for outputting a signal for requesting an interrupt to a respective one of said processors.
Claim 10
Dependent Claim
45 words
The apparatus of claim 8, wherein said interrupt generation circuit comprises a positive edge-triggered D type flip-flop for outputting said interrupt request signal when said positive edge-triggered D type flip-flop is set by said positive edge and reset by a respective one of said processors.
Claim 11
Dependent Claim
25 words
The apparatus of claim 6 further comprising an initialization prohibition means for prohibiting said logical one pulse to set said logical one to said flip-flop.
Claim 12
Dependent Claim
65 words
The apparatus of claim 10, wherein said initialization prohibition means comprising: a prohibition flag hold means being written a flag for prohibiting to initialize said prohibition flag hold means by a respective one of said processors; and an AND gate for inputting a logical AND between a value of said prohibition flag and said logical one pulse to said set terminal of said D flip-flop.
Claim 13
Dependent Claim
62 words
The apparatus of claim 1, wherein said flag has a value of one of a logical one and a logical zero, said logical one indicating an occurrence of an event in event synchronization and said logical zero indicating no event occurrence, and said control unit detects a change from said logical zero to said logical one, thereby outputting said logical one pulse.
Claim 14
Dependent Claim
61 words
The apparatus of claim 12, wherein said control unit comprising: an inverter for receiving a said synchronization signal from the lowermost stream synchronization unit and for outputting a logically reversed value, and a negative edge-triggered single shot circuit for outputting said logical one pulse when a negative edge is detected in a said synchronization signal sent from said lowermost-stream synchronization unit.
Claim 15
Dependent Claim
39 words
The apparatus of claim 12, wherein said control unit comprises a positive edge-triggered single shot circuit for outputting said logical one pulse when a positive edge is detected in a said synchronization signal sent from said lowermost-stream synchronization unit.
Claim 16
Dependent Claim
49 words
The apparatus of claim 13, wherein said logical OR means comprises an OR gate for receiving a said synchronization signal from an adjacent upstream synchronization unit and a value of said flag and for outputting a logical OR to an adjacent downstream synchronization unit as a said synchronization signal.
Claim 17
Dependent Claim
29 words
The apparatus of claim 15, wherein said flag hold means comprises a flip-flop for holding a value of said flag and for outputting said value to said OR gate.
Claim 18
Dependent Claim
73 words
The apparatus of claim 16, wherein said detection means comprises a positive edge triggered single shot circuit for outputting said pulse to said flip-flop when a positive edge is detected in a said logical OR outputted from said OR gate, and wherein said flip-flop comprises a set terminal for receiving an output of said positive edge triggered single shot circuit, said set terminal being set a logical one by said logical one pulse.
Claim 19
Dependent Claim
44 words
The apparatus of claim 17, wherein said output means comprises a tri-state buffer for receiving said logical OR from said logical OR means and for outputting an obtained value under a control of a read signal sent from a respective one of said processors.
Claim 20
Dependent Claim
39 words
The apparatus of claim 17, wherein said output means comprises an interrupt generation circuit for detecting said positive edge in the logical OR and for outputting a signal for requesting an interrupt to a respective one of said processors.
Claim 21
Dependent Claim
45 words
The apparatus of claim 19, wherein said interrupt generation circuit comprises a positive edge-triggered D type flip-flop for outputting said interrupt request signal when said positive edge-triggered D type flip-flop is set by said positive edge and reset by a respective one of said processors.
Claim 22
Dependent Claim
25 words
The apparatus of claim 17 further comprising an initialization prohibition means for prohibiting said logical one pulse to set said logical one to said flip-flop.
Claim 23
Dependent Claim
66 words
The apparatus of claim 21, wherein said initialization prohibition means comprises: a prohibition flag hold means for holding a prohibition flag for prohibiting initialization of said prohibition flag hold means by a respective one of said processors; and an AND gate for inputting a logical AND between a value of said prohibition flag and said logical one pulse to said set terminal of said D flip-flop.
Claim 24
Dependent Claim
108 words
The apparatus of claim 1 wherein said control unit comprises: an inverter for receiving a said synchronization signal from the lowermost stream synchronization unit and for outputting a logically reversed value; a switch for selecting one of a signal inputted to said inverter and a signal outputted from said inverter, thereby outputting a selected signal; and a negative edge-triggered single shot circuit for outputting said logical one pulse when a negative edge is detected in the selected signal outputted from said switch, wherein said switch selects said signal inputted to said inverter for a barrier synchronization and selects said signal outputted from said inverter for an event synchronization.
Claim 25
Dependent Claim
154 words
The apparatus of claim 1, wherein at least one of said synchronization units is a parallel synchronization unit, said parallel synchronization unit comprising: a plurality of synchronization flag hold units corresponding to said plurality of processors, respectively, each of said synchronization flag hold units holding a synchronization flag indicating a state of a respective one of said processors; a wired OR means for wired-ORing outputs of all the synchronization flag hold units; a logical OR means for ORing a said synchronization signal sent from an adjacent upstream synchronization unit with an output of said wired OR means and for outputting an obtained value to an adjacent downstream synchronization unit; and a plurality of synchronization detection units corresponding to said plurality of synchronization flag hold units, respectively, said synchronization detection units detecting said pulse in a said value outputted from said logical OR means, thereby initiating a respective one of said synchronization flag hold units.
Claim 26
Dependent Claim
83 words
The apparatus of claim 24, wherein said synchronization flag has a value of one of a logical one and a logical zero, said logical one indicating that a respective one of said processors is in operation and said logical zero indicating that a respective one of said processor is in a wait state, and said control means detects a change from said logical one to said logical zero, thereby outputting said pulse, said pulse being a logical one pulse with a fixed width.
Claim 27
Dependent Claim
79 words
The apparatus of claim 25, wherein said wired-OR means comprises: a plurality of open collector buffers corresponding to said plurality of synchronization flag hold units, respectively, each of said open collector buffers outputting a logical NOT of a respective one of said synchronization flag hold units; a wired-OR line for wired-ORing outputs of all the open collector buffers; and a NOT gate for outputting a logical NOT of an output of said wired-OR line to said logical OR means.
Claim 28
Dependent Claim
49 words
The apparatus of claim 26, wherein said logical OR means comprises an OR gate for receiving a said synchronization signal from an adjacent upstream synchronization unit and a value of said flag and for outputting a logical OR to an adjacent downstream synchronization unit as a said synchronization signal.
Claim 29
Dependent Claim
30 words
The apparatus of claim 27, wherein said synchronization flag hold means comprises a flip-flop for holding a value of said flag and for outputting said value to said OR gate.
Claim 30
Dependent Claim
74 words
The apparatus of claim 28, wherein said synchronization detection units comprises a positive edge triggered single shot circuit for outputting said pulse to said flip-flop when a positive edge is detected in a said logical OR outputted from said OR gate, and wherein said flip-flop comprises a set terminal for receiving an output of said positive edge triggered single shot circuit, said set terminal being set a logical one by said logical one pulse.
Claim 31
Dependent Claim
34 words
The apparatus of claim 29, wherein said parallel synchronization unit further comprises an output means for outputting a said synchronization signal sent from said logical OR means to at least one of said processors.
Claim 32
Dependent Claim
44 words
The apparatus of claim 30, wherein said output means comprises a tri-state buffer for receiving said logical OR from said logical OR means and for outputting an obtained value under a control of a read signal sent from a respective one of said processors.
Claim 33
Dependent Claim
39 words
The apparatus of claim 30, wherein said output means comprises an interrupt generation circuit for detecting said positive edge in the logical OR and for outputting a signal for requesting an interrupt to a respective one of said processors.
Claim 34
Dependent Claim
45 words
The apparatus of claim 32, wherein said interrupt generation circuit comprises a positive edge-triggered D type flip-flop for outputting said interrupt request signal when said positive edge-triggered D type flip-flop is set by said positive edge and reset by a respective one of said processors.
Claim 35
Dependent Claim
62 words
The apparatus of claim 24, wherein said flag has a value of one of a logical one and a logical zero, said logical one indicating an occurrence of an event in event synchronization and said logical zero indicating no event occurrence, and said control unit detects a change from said logical zero to said logical one, thereby outputting said logical one pulse.
Claim 36
Dependent Claim
79 words
The apparatus of claim 34, wherein said wired-OR means comprises: a plurality Of open collector buffers corresponding to said plurality of synchronization flag hold units, respectively, each of said open collector buffers outputting a logical NOT of a respective one of said synchronization flag hold units; a wired-OR line for wired-ORing outputs of all the open collector buffers; and a NOT gate for outputting a logical NOT of an output of said wired-OR line to said logical OR means.
Claim 37
Dependent Claim
49 words
The apparatus of claim 35, wherein said logical OR means comprises an OR gate for receiving a said synchronization signal from an adjacent upstream synchronization unit and a value of said flag and for outputting a logical OR to an adjacent downstream synchronization unit as a said synchronization signal.
Claim 38
Dependent Claim
30 words
The apparatus of claim 36, wherein said synchronization flag hold means comprises a flip-flop for holding a value of said flag and for outputting said value to said OR gate.
Claim 39
Dependent Claim
74 words
The apparatus of claim 37, wherein said synchronization detection units comprises a positive edge triggered single shot circuit for outputting said pulse to said flip-flop when a positive edge is detected in a said logical OR outputted from said OR gate, and wherein said flip-flop comprises a set terminal for receiving an output of said positive edge triggered single shot circuit, said set terminal being set a logical one by said logical one pulse.
Claim 40
Dependent Claim
34 words
The apparatus of claim 38, wherein said parallel synchronization unit further comprises an output means for outputting a said synchronization signal sent from said logical OR means to at least one, of said processors.
Claim 41
Dependent Claim
44 words
The apparatus of claim 39, wherein said output means comprises a tri-state buffer for receiving said logical OR from said logical OR means and for outputting an obtained value under a control of a read signal sent from a respective one of said processors.
Claim 42
Dependent Claim
39 words
The apparatus of claim 39, wherein said output means comprises an interrupt generation circuit for detecting said positive edge in the logical OR and for outputting a signal for requesting an interrupt to a respective one of said processors.
Claim 43
Dependent Claim
45 words
The apparatus of claim 41, wherein said interrupt generation circuit comprises a positive edge-triggered D type flip-flop for outputting said interrupt request signal when said positive edge-triggered D type flip-flop is set by said positive edge and reset by a respective one of said processors.
Claim 44
Independent Claim
215 words
An apparatus for synchronizing parallel processing among a plurality of processors, comprising: a control unit; and a plurality of synchronization units corresponding to the plurality of processors one to one, such that each processor has an associated synchronization unit, the control unit and the synchronization units being connected in a loop, wherein each of the synchronization units outputs a synchronization signal for notifying an adjacent downstream synchronization unit that said each synchronization unit has entered a wait state; and the control unit outputs a pulse for notifying an uppermost-stream synchronization unit that synchronization is complete among the processors, the pulse being forwarded as far as a lowermost-stream sychronization unit, wherein each of the synchronization units comprises: a flag holding means for holding a flag indicating a state of an associated processor; a logical OR means for ORing a synchronization signal sent from an adjacent upstream synchronization unit with a value of the flag and for outputting an obtained value to an adjacent downstream synchronization unit as a synchronization signal; a detection means for detecting the pulse outputted by the control unit in the synchronization signal outputted from the logical OR means, thereby initializing the flag holding means; and an output means for outputting the value outputted from the logical OR means to the associated processor.
Claim 45
Independent Claim
215 words
An apparatus for synchronizing parallel processing among a plurality of processors, comprising: a control unit; and a plurality of synchronization units corresponding to the plurality of processors one to one, such that each processor has an associated synchronization unit, the control unit and the synchronization units being connected in a loop, wherein each of the synchronization units outputs a synchronization signal for notifying an adjacent downstream synchronization unit that said each synchronization unit has entered a wait state; and the control unit outputs a pulse for notifying an uppermost-stream synchronization unit that synchronization is complete among the processors, the pulse being forwarded as far as a lowermost-stream sychronization unit, wherein each of the synchronization units comprises: a flag holding means for holding a flag indicating a state of an associated processor; a logical OR means for ORing a synchronization signal sent from an adjacent upstream synchronization unit with a value of the flag and for outputting an obtained value to an adjacent downstream synchronization unit as a synchronization signal; a detection means for detecting the pulse outputted by the control unit in the synchronization signal outputted from the logical OR means, thereby initializing the flag holding means; and an output means for outputting the value outputted from the logical OR means to the associated processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-21 | 1999-11-20 | 2000-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-21 | 2003-11-20 | 2004-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-21 | 2007-11-20 | 2008-05-21 | $7700.00 | Window Closed / Lapsed |