Apparatus and method for an address transition detector

Claim 2

An address transition detector comprising: a first pass gate coupled between an input terminal of said address transition detector unit and an output terminal of said address transition detection unit; a first delay unit coupled between an input terminal of said address transition detector unit and control terminals of said first pass gate, said first delay unit providing a first predetermined delay to a negative transition signal applied to said input terminal; a second pass gate coupled between said input terminal and said output terminal; and a second delay unit coupled between said input terminal and control terminals of said second pass gate, said second delay unit providing a second predetermined delay to a positive transition signal applied to said input terminal.

Claim 3

The address transition detector unit of claim 1 wherein said address transition detector unit is implemented in integrated circuit technology.

Claim 4

The address transition detector unit of claim 2 further comprising; a first inverting amplifier coupled between said input terminal and said second delay unit; and a second inverting amplifier coupled between said first inverting amplifier and said first delay unit.

Claim 5

The address transition detector unit of claim 3 wherein said first pass gate discharges a signal resulting from a short low-high-low duration input pulse, said second pass gate discharges a signal resulting from a long low-high-low duration input pulse.

Claim 6

The address transition detector unit of claim 2 wherein said first and said second predetermined delays are equal.

Claim 9

The method of claim 6 wherein said transmitting state includes the step of transmitting said leading edge transition through a first pass gate; and wherein said trapping step includes the step of disabling the conducting state of said first pass gate.

Claim 10

The method of claim 7 wherein said returning step includes the step of enabling a conducting state of said pass gate by output signals from a first delay unit responding to a trailing edge of said address transition, said output signals of said delay unit being generated after said predetermined period of time.

Claim 11

The method of claim 8 wherein said returning step includes the step of, for signals of long pulse width, generating control signals for a second pass gate in response to said leading edge transition, said control signals being generated a predetermined time after said leading edge transition by a second delay unit.

Claim 12

A pulse signal detector comprising: first trapping means for transmitting to an output terminal an input signal resulting from a first polarity transition signal applied to an input terminal of said pulse signal detector, said first trapping means trapping a first resulting signal for a first predetermined period of time in response to first control signals on an output terminal of said pulse signal detector, wherein at least one of said first control signals has said first predetermined period of time with respect to said first polarity transition signal; first control signal means for providing said first control signals in response to said first polarity transition; second trapping means for transmitting to said output terminal an input signal resulting from a second polarity transition signal applied to said input terminal, said second trapping means trapping a second resulting signal for a second predetermined period of time in response to second control signals, wherein at least one of said second control signals having said second predetermined delay with respect to said second polarity transition signal; and second control signal means for providing said second control signals in response to said second polarity transition signal.

Claim 13

A pulse signal detector comprising: first trapping means for transmitting to an output terminal an input signal resulting from a first polarity transition signal applied to an input terminal of said pulse signal detector, said first trapping means trapping a first resulting signal for a first predetermined period of time in response to first control signals on an output terminal of said pulse signal detector, wherein at least one of said first control signals has said first predetermined period of time with respect to said first polarity transition signal; first control signal means for providing said first control signals in response to said first polarity transition; second trapping means for transmitting to said output terminal an input signal resulting from a second polarity transition signal applied to said input terminal, said second trapping means trapping a second resulting signal for a second predetermined period of time in response to second control signals, wherein at least one of said second control signals having said second predetermined delay with respect to said second polarity transition signal; and second control signal means for providing said second control signals in response to said second polarity transition signal.

Claim 14

The pulse signal detector unit of claim 10 wherein said detector is implemented in integrated circuit technology.

Claim 15

The pulse signal detector unit of claim 11 wherein said first trapping means includes a pass gate component responsive to said first control signals, and wherein said second trapping means includes a second pass gate component responsive to said second control signals.

Claim 16

The pulse signal detector unit of claim 12 wherein said first control signal means includes a first delay component responsive to said first polarity transition signal for providing said first control signal with said first predetermined delay, wherein said second control means includes a second delay component for providing said second control signal with said second predetermined delay.

Claim 17

The pulse signal detector unit of claim 13 wherein said each delay component includes; a first transistor coupled to ground; second transistor coupled to a supply voltage; a resistor coupled between said first transistor and said second transistor, wherein a input terminal is coupled to control terminals of said first and said second transistors; a capacitor coupled in parallel with said first transistor; and an inverting amplifier having an input terminal coupled to a non-grounded capacitor terminal, an output terminal of said inverting amplifier being an output terminal of said delay unit.

Claim 18

The pulse detector unit of claim 10 wherein said first predetermined period and said second predetermined period are equal.