Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test

Claim 2

A semiconductor memory device including a plurality of word lines, a plurality of bit lines crossing respective word lines, and a plurality of memory cell transistors each connected to one of said plurality of word lines and one of said plurality of bit lines, and incorporating a test circuit for determining in a test mode a memory cell transistor having an absolute value of a threshold voltage lower than a predetermined threshold voltage among said plurality of memory cell transistors, comprising: a word line for test provided in parallel with said plurality of word lines, crossing said plurality of bit lines, and coupled to respective bit lines with parasitic capacitance; test mode detecting means for detecting said test mode; and small signal generating means responsive to detection of the test mode by said test mode detecting means for applying a small signal, having a changing amplitude , to said word line for test for increasing the potential thereof.

Claim 3

A semiconductor memory device including a plurality of word lines, a plurality of bit lines crossing respective word lines, and a plurality of memory cell transistors each connected to one of said plurality of word lines and one of said plurality of bit lines, and incorporating a test circuit for determining in a test mode a memory cell transistor having an absolute value of a threshold voltage lower than a predetermined threshold voltage among said plurality of memory cell transistors, comprising: a word line for test provided in parallel with said plurality of word lines, crossing said plurality of bit lines, and coupled to respective bit lines with parasitic capacitance; test mode detecting means for detecting said test mode; small signal generating means responsive to detection of the test mode by said test mode detecting means for applying a small signal, having a changing amplitude, to said word line for test for increasing the potential thereof; and a switching element connected between bit lines crossing said word line for test and a plurality of bit lines connected to said memory cell transistors, rendered non-conductive in a write/read mode for writing data to any of said plurality of memory cell transistors or for reading out written data, and rendered conductive in response to said test mode.

Claim 4

A semiconductor memory device including a plurality of word lines, a plurality of bit lines crossing respective word lines, and a plurality of memory cell transistors each connected to one of said plurality of word lines and one of said plurality of bit lines, and incorporating a test circuit for determining in a test mode a memory cell transistor having an absolute value of a threshold voltage lower than a predetermined threshold voltage among said plurality of memory cell transistors, comprising: a word line for test provided in parallel with said plurality of word lines, crossing said plurality of bit lines, and coupled to respective bit lines with parasitic capacitance; test mode detecting means for detecting said test mode; small signal generating means responsive to detection of the test mode by said test mode detecting means for applying a small signal, having a changing amplitude, to said word line for test for increasing the potential thereof; and a switching element connected between bit lines crossing said word line for test and a plurality of bit lines connected to said memory cell transistors, rendered non-conductive in a write/read mode for writing data to any of said plurality of memory cell transistors or for reading out written data, and rendered conductive in response to said test mode.

Claim 5

The semiconductor memory device as recited in claim 1, wherein said test mode detecting means includes means for detecting said test mode based on an address signal for designating an address of each of said memory cell transistors and an address strobe signal.