US5519333A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Elevated voltage level IDDQ failure testing of integrated circuits
Assignee: ENERGY DEPARTMENT OF United States, THE, Secretary of
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Filing: 1994-09-09
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Granted: 1996-05-21
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Expires: 2014-09-09
Abstract
Abstract Burn in testing of static CMOS IC's is eliminated by I DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.
Inventors
- 👤 Alan W. Righter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3004; G01R31/3008
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
135 words
A method for failure testing fully static CMOS integrated circuits (IC) having a plurality of nodes comprising: stress testing the integrated circuit with a vector set of voltage inputs to the supply and input pins of the IC which toggles a maximum number of nodes in the IC on and off and tests a maximum number of bridges between nodes by driving the nodes on either side of the bridge to opposite logic values, the vector set of voltage inputs for this stress test being at least 25% higher than the normal voltages to the respective pins; measuring the quiescent supply current (I DDQ ) during the stress test of the IC; and identifying failed IC's by the amount the I DDQ measured during the stress test exceeds a known value derived from good IC's.
Claim 2
Independent Claim
135 words
A method for failure testing fully static CMOS integrated circuits (IC) having a plurality of nodes comprising: stress testing the integrated circuit with a vector set of voltage inputs to the supply and input pins of the IC which toggles a maximum number of nodes in the IC on and off and tests a maximum number of bridges between nodes by driving the nodes on either side of the bridge to opposite logic values, the vector set of voltage inputs for this stress test being at least 25% higher than the normal voltages to the respective pins; measuring the quiescent supply current (I DDQ ) during the stress test of the IC; and identifying failed IC's by the amount the I DDQ measured during the stress test exceeds a known value derived from good IC's.
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein the method is sufficiently accurate that burn-in testing of the IC is unnecessary and not performed as an additional step.
Claim 4
Dependent Claim
25 words
The method of claim 1, wherein individual values of I DDQ are measured for at least some of the individual vectors in the vector set.
Claim 5
Dependent Claim
18 words
The method of claim 1, wherein the stressing voltage is at least 50% higher than the normal voltage.
Claim 6
Dependent Claim
24 words
The method of claim 1, wherein the stressing voltage is less than a voltage level which will cause overstress of an otherwise good IC.
Claim 7
Dependent Claim
32 words
The method of claim 1, wherein the stress test of the IC by the vector set is preceded by a test of the IC by the vector set using normal voltage levels.
Claim 8
Dependent Claim
32 words
The method of claim 6, wherein the measured values of I DDQ for the stress test and the test at normal voltage levels are used to identify a failure in the IC.
Claim 9
Dependent Claim
32 words
The method of claim 1, wherein the stress test of the IC by the vector set is followed by a test of the IC by the vector set using normal voltage levels.
Claim 10
Dependent Claim
32 words
The method of claim 8, wherein the measured values of I DDQ for the stress test and the test at normal voltage levels are used to identify a failure in the IC.
Claim 11
Dependent Claim
13 words
The method of claim 1, wherein the stress test is run multiple times.
Claim 12
Dependent Claim
15 words
The method of claim 10, wherein the multiple runs are conducted at different stressing voltages.
Claim 13
Dependent Claim
21 words
The method of claim 10, wherein the multiple runs of the stress test are done in less than about 2 minutes.
Claim 14
Dependent Claim
14 words
The method of claim 1, wherein the test is conducted at an elevated temperature.
Claim 15
Dependent Claim
28 words
The method of claim 1, wherein the IC is considered as failed if any value of I DDQ measured during or after a stress test exceeds 700 nA.
Claim 16
Dependent Claim
17 words
The method of claim 1 wherein the integrated circuit is presented in a die on a wafer.
Claim 17
Dependent Claim
16 words
The method of claim 1 wherein the integrated circuit is presented as devices in a package.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-21 | 1999-11-20 | 2000-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-21 | 2003-11-20 | 2004-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-21 | 2007-11-20 | 2008-05-21 | $7700.00 | Window Closed / Lapsed |